6 CardBus Socket Registers (Functions 0 and 1)
The 1997 PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and
control socket-specific functions. The PCI6x21/PCI6x11 controller provides the CardBus socket/ExCA base address
register (PCI offset 10h, see Section 4.12) to locate these CardBus socket registers in PCI memory address space.
Each function has a separate base address register for accessing the CardBus socket registers (see Figure 6−1).
Table 6−1 gives the location of the socket registers in relation to the CardBus socket/ExCA base address.
In addition to the five required registers, the PCI6x21/PCI6x11 controller implements a register at offset 20h that
provides power management control for the socket.
Host
Memory Space
Host
Memory Space
PCI6x21/PCI6x11 Configuration Registers
Offset
00h
Offset
Offset
CardBus
Socket A
Registers
10h
44h
CardBus Socket/ExCA Base Address
16-Bit Legacy-Mode Base Address
20h
00h
CardBus
Socket B
Registers
800h
ExCA
Registers
Card A
20h
844h
800h
ExCA
Registers
Card B
Note: The CardBus socket/ExCA base
address mode register is separate for
functions 0 and 1.
844h
Offsets are from the CardBus socket/ExCA base
address register’s base address.
Figure 6−1. Accessing CardBus Socket Registers Through PCI Memory
Table 6−1. CardBus Socket Registers
REGISTER NAME
OFFSET
00h
Socket event †
Socket mask †
04h
Socket present state †
Socket force event
Socket control †
08h
0Ch
10h
Reserved
14h−1Ch
20h
Socket power management ‡
†
‡
One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.
One or more bits in this register are cleared only by the assertion of GRST.
6−1
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