List of Illustrations
Figure
2–1
2–2
3–1
3–2
3–3
3–4
3–5
6–1
6–2
6–3
6–4
Title
Page
PCI2250 PGF LQFP Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
PCI2250 PCM PQFP Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
PCI AD31–AD0 During Address Phase of a Type 0 Configuration Cycle 3–2
PCI AD31–AD0 During Address Phase of a Type 1 Configuration Cycle 3–3
Bus Hierarchy and Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Secondary Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Load Circuit and Voltage Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
PCLK Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
RSTIN Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Shared-Signals Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
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TI [ TEXAS INSTRUMENTS ]
