REMOTE 8-BIT I
2
C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
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A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
Start Condition
P
Stop Condition
Figure 1. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Change
Figure 2. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
S
Start
Condition
1
2
8
9
Clock Pulse for
Acknowledgment
Figure 3. Acknowledgment on the I
2
C Bus
Interface Definition
BYTE
I
2
C slave address
Px I/O data bus
BIT
7 (MSB)
L
P7
6
L
P6
5
H
P5
4
H
P4
3
A2
P3
2
A1
P2
1
A0
P1
0 (LSB)
R/W
P0
6
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