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REMOTE 8-BIT I C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
2
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
SIMPLIFIED SCHEMATIC OF P1 TO P7
Data From
Shift Register
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Configuration
Register
D
Q
FF
C
K
Q
D
Q
FF
Output Port
Register Data
V
CC
P1 to P7
ESD Protection Diode
Input
Port
Register
D
Q
FF
GND
Input Port
Register Data
C
K
Q
Output
Port
Register
Read Pulse
C
K
Q
Data From
Shift Register
Write Polarity Pulse
D
Q
FF
Polarity
Register Data
C
K
Q
Polarity
Inversion
Register
A.
On power up or reset, all registers return to default values.
I
2
C Interface
The bidirectional I
2
C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I
2
C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see
After the Start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device
must not be changed between the Start and the Stop conditions.
On the I
2
C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see
Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
5
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