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REMOTE 8-BIT I C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
2
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
Interrupt (INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, t
iv
, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt or in a Stop event. Resetting occurs in the read
mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. In a
Stop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clock
pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the
I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the Input Port Register.
The INT output has an open-drain structure and requires pullup resistor to V
CC
.
Bus Transactions
Data is exchanged between the master and PCA6107 through write and read commands.
Writes
Data is transmitted to the PCA6107 by sending the device address and setting the least-significant bit to a logic
0 (see
for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one
write transmission.
SCL
1
2
3
4
5
6
7
8
9
Command Byte
A
0
0
0
0
0
0
0
1
A
Data to Port
Data 1
A
P
Slave Address
SDA
S
0
0
1
1 A2 A1 A0 0
Start Condition
Write to Port
R/W ACK From Slave
ACK From Slave
ACK From Slave
Data Out
From Port
t
pv
Data 1 Valid
Figure 6. Write to Output Port Register
<br/>
SCL
1
2
3
4
5
6
7
8
9
Command Byte
A
0
0
0
0
0
0
0 1/0 A
Data to Register
Data
A
P
Slave Address
SDA
S
0
0
1
1 A2 A1 A0 0
R/W
Start Condition
ACK From Slave
ACK From Slave
ACK From Slave
Figure 7. Write to Configuration or Polarity Inversion Registers
9
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