OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
Table 6-71. eHRPWM Module Control and Status Registers Grouped by Submodule (continued)
eHRPWM1
BYTE ADDRESS BYTE ADDRESS
eHRPWM2
eHRPWM3
BYTE ADDRESS Acronym
Size Shad
(×16) ow
Register Description
Action-Qualifier Submodule Registers
0x01F0 0016
0x01F0 0018
0x01F0 2016
0x01F0 2018
0x01F0 4016
0x01F0 4018
AQCTLA
1
No
No
No
Action-Qualifier Control Register for
Output A (eHRPWMxA)
AQCTLB
1
Action-Qualifier Control Register for
Output B (eHRPWMxB)
0x01F0 001A
0x01F0 001C
0x01F0 201A
0x01F0 201C
0x01F0 401A
0x01F0 401C
AQSFRC
1
1
Action-Qualifier Software Force Register
AQCSFRC
Yes Action-Qualifier Continuous S/W Force
Register Set
Dead-Band Generator Submodule Registers
0x01F0 001E
0x01F0 0020
0x01F0 201E
0x01F0 2020
0x01F0 401E
0x01F0 4020
DBCTL
DBRED
1
1
No
No
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge
Delay Count Register
0x01F0 0022
0x01F0 003C
0x01F0 2022
0x01F0 203C
0x01F0 4022
0x01F0 403C
DBFED
1
No
Dead-Band Generator Falling Edge
Delay Count Register
PWM-Chopper Submodule Registers
PCCTL
1
No
PWM-Chopper Control Register
Trip-Zone Submodule Registers
0x01F0 0024
0x01F0 0028
0x01F0 002A
0x01F0 002C
0x01F0 002E
0x01F0 0030
0x01F0 2024
0x01F0 2028
0x01F0 202A
0x01F0 202C
0x01F0 202E
0x01F0 2030
0x01F0 4024
0x01F0 4028
0x01F0 402A
0x01F0 402C
0x01F0 402E
0x01F0 4030
TZSEL
TZCTL
TZEINT
TZFLG
TZCLR
TZFRC
1
1
1
1
1
1
No
No
No
No
No
No
Trip-Zone Select Register
Trip-Zone Control Register
Trip-Zone Enable Interrupt Register
Trip-Zone Flag Register
Trip-Zone Clear Register
Trip-Zone Force Register
Event-Trigger Submodule Registers
0x01F0 0032
0x01F0 0034
0x01F0 0036
0x01F0 0038
0x01F0 003A
0x01F0 2032
0x01F0 2034
0x01F0 2036
0x01F0 2038
0x01F0 203A
0x01F0 4032
0x01F0 4034
0x01F0 4036
0x01F0 4038
0x01F0 403A
ETSEL
ETPS
1
1
1
1
1
No
No
No
No
No
Event-Trigger Selection Register
Event-Trigger Pre-Scale Register
Event-Trigger Flag Register
Event-Trigger Clear Register
Event-Trigger Force Register
ETFLG
ETCLR
ETFRC
High-Resolution PWM (HRPWM) Submodule Registers
HRCNFG No HRPWM Configuration Register
(1)
0x01F0 1020
0x01F0 3020
0x01F0 5020
1
6.20 Enhanced Pulse Width Modulator (eHRPWM) Timing
PWM refers to PWM outputs on eHRPWM1-6. Table 6-72 shows the PWM timing requirements and
Table 6-73, switching characteristics.
Table 6-72. eHRPWM Timing Requirements
TEST CONDITIONS
Asynchronous
MIN
2tc(SCO)
MAX
UNIT
cycles
cycles
cycles
tw(SYCIN)
Sync input pulse width
Synchronous
2tc(SCO)
With input qualifier
1tc(SCO) + tw(IQSW)
Table 6-73. eHRPWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
td(PWM)tza
8tc(SCO)
cycles
ns
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
no pin load
25
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