OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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Table 6-31. EMAC Control Module Registers (continued)
BYTE ADDRESS
Acronym
Register Description
0x01E2 206C
C2MISCSTAT
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status
Register
0x01E2 2070
0x01E2 2074
0x01E2 2078
0x01E2 207C
0x01E2 2080
0x01E2 2084
C0RXIMAX
C0TXIMAX
C1RXIMAX
C1TXIMAX
C2RXIMAX
C2TXIMAX
EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond
Register
EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond
Register
EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond
Register
EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond
Register
EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond
Register
EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond
Register
Table 6-32. EMAC Control Module RAM
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
EMAC Local Buffer Descriptor Memory
0x01E2 0000 - 0x01E2 1FFF
Table 6-33. RMII Timing Requirements
NO.
PARAMETER
MIN
TYP
MAX
UNIT
ns
1
tc(REFCLK)
Cycle Time, REF_CLK
Pulse Width, REF_CLK High
Pulse Width, REF_CLK Low
20
2
3
6
tw(REFCLKH)
tw(REFCLKL)
tsu(RXD-REFCLK)
7
7
4
13
13
ns
ns
Input Setup Time, RXD Valid before REF_CLK
High
ns
7
8
th(REFCLK-RXD)
Input Hold Time, RXD Valid after REF_CLK High
2
4
ns
ns
tsu(CRSDV-REFCLK)
Input Setup Time, CRSDV Valid before
REF_CLK High
9
th(REFCLK-CRSDV)
tsu(RXER-REFCLK)
th(REFCLKR-RXER)
Input Hold Time, CRSDV Valid after REF_CLK
High
2
4
2
ns
ns
ns
10
11
Input Setup Time, RXER Valid before REF_CLK
High
Input Hold Time, RXER Valid after REF_CLK
High
Table 6-34. RMII Timing Requirements
NO.
4
PARAMETER
MIN
TYP
MAX
13
UNIT
ns
td(REFCLK-TXD)
td(REFCLK-TXEN)
Output Delay Time, REF_CLK High to TXD Valid
2.5
2.5
5
Output Delay Time, REF_CLK High to TXEN
Valid
13
ns
126
Peripheral Information and Electrical Specifications
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