XIO3130
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SLLS693F–MAY 2007–REVISED JANUARY 2010
PCI Express Differential Receiver Input Ranges (continued)
PARAMETER
TERMINALS
MIN NOM
MAX UNIT
COMMENTS
Measured over 50 MHz to 1.25 GHz with the P
and N lines biased at +300 mV and –300 mV,
respectively.
RLRX-DIFF
Differential return loss
PERP,
PERN
10
dB
(4)
See
Measured over 50 MHz to 1.25 GHz with the P
and N lines biased at +300 mV and –300 mV,
RLRX-CM
Common mode return loss
PERP,
PERN
6
dB
respectively.
(4)
See
.
ZRX-DIFF-DC
DC differential input impedance
PERP,
PERN
RX DC differential mode impedance.
80
40
100
50
120
60
Ω
Ω
(5)
See
.
Required RX-D+ as well as RX-D– DC impedance
ZRX-DC
DC input impedance
PERP,
PERN
(50 Ω ±20% tolerance).
(5)
See (1) and
.
Required RX-D+ as well as RX-D– DC impedance
ZRX-HIGH-IMP-DC
Powered-down DC input impedance
PERP,
PERN
200K
65
Ω
when the receiver terminations do not have power.
(6)
See
.
VRX-IDLE-DET-DIFFp-p
Electrical idle detect threshold
PERP,
PERN
VRX-IDLE-DET-DIFFp-p = 2 * |VRX-D+ – VRX-D–
|
175
10
mV
measured at the receiver package pins
An unexpected electrical idle (VRX-DIFFp-p
<
TRX-IDLE-DET-DIFF-ENTER-TIME
Unexpected electrical idle enter
detect threshold integration time
VRX-IDLE-DET-DIFFp-p) must be recognized no longer
than
TRX-IDLE-DET-DIFF-ENTER-TIME to signal an
unexpected idle condition.
PERP,
PERN
ms
(4) The Receiver input impedance shall result in a differential return loss greater than or equal to 10 dB with a differential test input signal of
no less than 200 mV (peak value, 400 mV differential peak to peak) swing around ground applied to D+ and D– lines and a common
mode return loss greater than or equal to 6 dB (no bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance
requirement applies to all valid input levels. The reference impedance for return loss measurements for is 50 Ω to ground for both the
D+ and D– line (i.e., as measured by a Vector Network Analyzer with 50 Ω probes; see Figure 4-25 in the specification). Note that the
series capacitors CTX is optional for the return loss measurement.
(5) Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM) there is a 5
ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
(6) The RX DC common mode impedance that exists when no power is present or Fundamental Reset is asserted. This helps ensure that
the Receiver Detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 200 mV
above the RX ground.
6.5 PCI Express Differential Reference Clock Input Ranges(1)
PARAMETER
TERMINALS
MIN NOM
MAX UNIT
COMMENTS
fIN-DIFF
REFCKIp
REFCKIn
The input frequency is 100 MHz +300 ppm and
–2800＝ppm including SSC-dictated variations.
100
MHz
Differential input frequency
VRX-DIFFp-p
Differential input peak-to-peak
voltage
REFCKIp
REFCKIn
0.175
1.2
V
VRX-DIFFp-p = 2*|VREFCKp – VREFCKn|
VRX-CM-ACp
AC peak common mode input
voltage
VRX-CM-ACp = RMS(|VREFCKp + VREFCKn|/2 –
VRX-CM-DC)
VRX-CM-DC = DC(avg) of |VREFCKp + VREFCKn|/2
REFCKIp
REFCKIn
140
mV
REFCKIp
REFCKIn
Duty cycle
40%
60%
Differential waveform input duty cycle
ZRX-DIFF-DC
DC differential input impedance
REFCKIp
REFCKIn
REFCKIp/ REFCKIn DC differential mode
impedance
20
kΩ
(1) The XIO3130 is compliant with the defined system jitter models for a PCI Express reference clock and associated TX/RX link. These
system jitter models are described in the PCI Express Jitter Modeling, Revision 1.0RD document. Any usage of the XIO3130 in a
system configuration that does not conform to the defined system jitter models requires the system designer to validate the system jitter
budgets.
Copyright © 2007–2010, Texas Instruments Incorporated
Electrical Characteristics
137
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