XIO3130
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SLLS693F–MAY 2007–REVISED JANUARY 2010
6.7 3.3-V I/O Electrical Characteristics(1)
PARAMETER
High-level input voltage(2)
Low-level input voltage(2)
Input voltage
OPERATIONS
TEST CONDITIONS
MIN
MAX
VDD33
UNIT
V
VIH
VIL
VI
VDD33
VDD33
0.7 VDD33
0
0
0
0
0.3 VDD33
VDD33
V
V
VO
tp
Output voltage(3)
VDD33
V
Input transition time (trise and tfall)
Input hysteresis(4)
25
ns
V
Vhys
VOH
VOL
IOZ
0.13 VDD33
High-level output voltage
Low-level output voltage
VDD33
VDD33
VDD33
IOH = –4 mA
IOL = 4 mA
0.8 VDD33
V
0.22 VDD33
±20
V
(3)
High-impedance, output current
VI = 0 to VDD33
mA
High-impedance, output current with internal
pullup or pulldown resistor
IOZP
II
VDD33
VDD33
VI = 0 to VDD33
VI = 0 to VDD33
±175
±1
mA
mA
(5)
(6)
Input current
(1) This table applies to PERST, WAKE, REFCLK_SEL, GRST, and GPIO18:0.
(2) Applies to external inputs and bidirectional buffers.
(3) Applies to external outputs and bidirectional buffers.
(4) Applies to PERST and GRST.
(5) Applies to GRST (pullup resistor) and most GPIO (pullup resistor).
(6) Applies to external input buffers.
6.8 POWER CONSUMPTION(1)
PARAMETER
MIN
NOM(2)
MAX(3)
20.61
UNIT
I3.3V
11.21
578.7
36.99
868.05
5.28
mA
mA
mW
mW
mA
I1.5V
725.8
P3.3V
68.01
P1.5V
1088.7
(4)
IAUX
(1) Measurements taken at 25°C with nominal power supply, 3.3 V and 1.5 V.
(2) Nominal conditions are defined as switch only power, no devices downstream, and downstream clocks not running.
(3) Maximum power conditions are defined as three downstream devices constantly running traffic and downstream clocks running.
(4) Measurement performed with three devices downstream, system in S5.
6.9 THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS(1)
Low K JEDEC test board, 1s (single-signal layer), no air flow
No air flow
TYP
51.2
30.5
17.7
14.7
7
UNIT
qJA
Junction-to-free-air thermal resistance
°C/W
High K JEDEC test board, 2s2p
(double-signal layer, double buried power plane)
400 LFM
200 LFM
Cu cold plate measurement process
EIA/JESD 51-8
qJC
qJB
Junction-to-case thermal resistance
Junction-to-board thermal resistance
Junction-to-top of package
Junction-to-board
°C/W
°C/W
°C/W
°C/W
13.9
0.5
ΨJT
ΨJB
EIA/JESD 51-2
EIA/JESD 51-6
12
(1) For more details, refer to TI application report IC Package Thermal Metrics (literature number SPRA953).
Copyright © 2007–2010, Texas Instruments Incorporated
Electrical Characteristics
139
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