MSP430G2955
MSP430G2855
MSP430G2755
SLAS800 –MARCH 2013
www.ti.com
Table 2. Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
DA
RHA
P1.0/
General-purpose digital I/O pin
TACLK/
ADC10CLK
P1.1/
31
29
I/O
Timer_A, clock signal TACLK input
ADC10, conversion clock
General-purpose digital I/O pin
32
33
34
30
31
32
I/O
I/O
I/O
TA0.0
P1.2/
Timer_A, capture: CCI0A input, compare: OUT0 output or BSL transmit
General-purpose digital I/O pin
TA0.1
P1.3/
Timer_A, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
TA0.2
P1.4/
Timer_A, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
SMCLK/
TCK
35
36
33
34
I/O
I/O
SMCLK signal output
JTAG test clock, input terminal for device programming and test
General-purpose digital I/O pin
P1.5/
TA0.0/
TMS
Timer_A, compare: OUT0 output
JTAG test mode select, input terminal for device programming and test
General-purpose digital I/O pin /
P1.6/
TA0.1/
TDI/
Timer_A, compare: OUT1 output
37
38
8
35
36
6
I/O
I/O
I/O
JTAG test data input terminal during programming and test
JTAG test clock input terminal during programming and test
General-purpose digital I/O pin
TCLK
P1.7/
TA0.2/
TDO/
TDI(1)
Timer_A, compare: OUT2 output
JTAG test data output terminal during programming and test
JTAG test data input terminal during programming and test
General-purpose digital I/O pin
P2.0/
TA1CLK/
ACLK/
A0
Timer1_A3.TACLK
ACLK output
ADC10, analog input A0
P2.1/
General-purpose digital I/O pin
TAINCLK/
SMCLK/
A1
Timer_A, clock signal at INCLK
9
7
8
I/O
I/O
SMCLK signal output
ADC10, analog input A1
P2.2/
General-purpose digital I/O pin
TA0.0/
A2
10
Timer_A, capture: CCI0B input or BSL receive, compare: OUT0 output
ADC10, analog input A2
P2.3/
General-purpose digital I/O pin
TA0.1/
A3/
Timer_A, capture CCI1B input, compare: OUT1 output
ADC10, analog input A3
29
30
27
28
I/O
I/O
VREF-/
VEREF-
P2.4/
Negative reference voltage output
Negative reference voltage input
General-purpose digital I/O pin
TA0.2/
A4/
Timer_A, compare: OUT2 output
ADC10, analog input A4
VREF+/
VEREF+
Positive reference voltage output
Positive reference voltage input
(1) TDO or TDI is selected via JTAG instruction.
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