MSP430G2955
MSP430G2855
MSP430G2755
SLAS800 –MARCH 2013
www.ti.com
Table 1. Available Options(1)(2)
Flash
(KB)
RAM
(B)
Timer_A
Timer_B
COMP_A+
Channels
ADC10
Channels
USCI_A0
USCI_B0
Package
Type
Device
BSL
EEM
Clock
I/O
MSP430G2955IDA38
MSP430G2955IRHA40
MSP430G2855IDA38
MSP430G2855IRHA40
MSP430G2755IDA38
MSP430G2755IRHA40
HF, LF,
DCO,
VLO
32
32
32
32
32
32
38-TSSOP
40-QFN
2x TA3
1x TB3
1
1
56
48
32
4096
4096
4096
8
8
8
12
12
12
1
1
1
HF, LF,
DCO,
VLO
38-TSSOP
40-QFN
2x TA3
1x TB3
1
1
1
1
HF, LF,
DCO,
VLO
38-TSSOP
40-QFN
2x TA3
1x TB3
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Device Pinout, 38-Pin TSSOP (DA Package)
TEST/SBWTCK
DVCC
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P1.7/TA0.2/TDO/TDI
P1.6/TA0.1/TDI
2
P2.5/TA1.0/ROSC
DVSS
3
P1.5/TA0.0/TMS
4
P1.4/SMCLK/TCK
XOUT/P2.7
5
P1.3/TA0.2
XIN/P2.6
6
P1.2/TA0.1
RST/NMI/SBWTDIO
P2.0/TA1CLK/ACLK/A0
P2.1/TA0INCLK/SMCLK/A1
P2.2/TA0.0/A2
7
P1.1/TA0.0
8
P1.0/TA0CLK/ADC10CLK
P2.4/TA0.2/A4/VREF+/VEREF+
P2.3/TA0.1/A3/VREF−/VEREF−
P3.7/TA1.2/A7
9
10
11
12
13
14
15
16
17
18
19
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
AVSS
P3.6/TA1.1/A6
P3.5/UCA0RXD/UCA0SOMI
P3.4/UCA0TXD/UCA0SIMO
P4.7/TB0CLK/CA7
P4.6/TB0OUTH/A15/CA6
P4.5/TB0.2/A14/CA5
P4.4/TB0.1/A13/CA4
P4.3/TB0.0/A12/CA3
AVCC
P4.0/TB0.0/CA0
P4.1/TB0.1/CA1
P4.2/TB0.2/CA2
2
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