MSP430G2x53
MSP430G2x13
SLAS735A
–
APRIL 2011
–
REVISED MAY 2011
Table 2. Terminal Functions
TERMINAL
NO.
NAME
P1.0/
TA0CLK/
ACLK/
A0
CA0
P1.1/
TA0.0/
UCA0RXD/
UCA0SOMI/
A1/
CA1
P1.2/
TA0.1/
UCA0TXD/
UCA0SIMO/
A2/
CA2
P1.3/
ADC10CLK/
A3/
VREF-/VEREF-/
CA3/
CAOUT
P1.4/
SMCLK/
UCB0STE/
UCA0CLK/
A4/
VREF+/VEREF+/
CA4/
TCK
P1.5/
TA0.0/
UCB0CLK/
UCA0STE/
A5/
CA5/
TMS
7
7
5
I/O
6
6
4
I/O
5
5
3
I/O
4
4
2
I/O
3
3
1
I/O
2
2
31
I/O
PW20,
N20
PW28
RHB32
General-purpose digital I/O pin
Timer0_A, clock signal TACLK input
ACLK signal output
ADC10 analog input A0
(1)
Comparator_A+, CA0 input
General-purpose digital I/O pin
Timer0_A, capture: CCI0A input, compare: Out0 output
USCI_A0 receive data input in UART mode,
USCI_A0 slave data out/master in SPI mode
ADC10 analog input A1
(1)
Comparator_A+, CA1 input
General-purpose digital I/O pin
Timer0_A, capture: CCI1A input, compare: Out1 output
USCI_A0 transmit data output in UART mode,
USCI_A0 slave data in/master out in SPI mode,
ADC10 analog input A2
(1)
Comparator_A+, CA2 input
General-purpose digital I/O pin
ADC10, conversion clock output
(1)
ADC10 analog input A3
(1)
ADC10 negative reference voltage
Comparator_A+, CA3 input
Comparator_A+, output
General-purpose digital I/O pin
SMCLK signal output
USCI_B0 slave transmit enable
USCI_A0 clock input/output
ADC10 analog input A4
(1)
ADC10 positive reference voltage
(1)
Comparator_A+, CA4 input
JTAG test clock, input terminal for device programming and test
General-purpose digital I/O pin
Timer0_A, compare: Out0 output
USCI_B0 clock input/output,
USCI_A0 slave transmit enable
ADC10 analog input A5
(1)
Comparator_A+, CA5 input
JTAG test mode select, input terminal for device programming and test
(1)
I/O
DESCRIPTION
(1)
MSP430G2x53 devices only
5
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2011, Texas Instruments Incorporated
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