MSP430G2x53
MSP430G2x13
SLAS735A
–
APRIL 2011
–
REVISED MAY 2011
Functional Block Diagram, MSP430G2x53
XIN XOUT
DVCC
DVSS
P1.x
8
P2.x
8
P3.x
8
ACLK
Clock
System
MCLK
Flash
SMCLK
16KB
8KB
4KB
2KB
MAB
MDB
RAM
512B
256B
10-Bit
8 Ch.
Autoscan
1 ch DMA
ADC
Port P1
8 I/O
Interrupt
capability
pullup/down
resistors
Port P2
8 I/O
Interrupt
capability
pullup/down
resistors
Port P3
8 I/O
pullup/
pulldown
resistors
16MHz
CPU
incl. 16
Registers
Emulation
2BP
JTAG
Interface
Spy-Bi-
Wire
RST/NMI
Brownout
Protection
Comp_A+
8 Channels
Watchdog
WDT+
15-Bit
Timer0_A3
3 CC
Registers
Timer1_A3
3 CC
Registers
USCI A0
UART/
LIN, IrDA,
SPI
USCI B0
SPI, I2C
NOTE: Port P3 is available on 28-pin and 32-pin devices only.
Functional Block Diagram, MSP430G2x13
XIN XOUT
DVCC
DVSS
P1.x
8
P2.x
8
P3.x
8
ACLK
Clock
System
MCLK
SMCLK
Flash
RAM
16KB
8KB
4KB
2KB
MAB
MDB
512B
256B
Port P1
8 I/O
Interrupt
capability
pullup/down
resistors
Port P2
8 I/O
Interrupt
capability
pullup/down
resistors
Port P3
8 I/O
pullup/
pulldown
resistors
16MHz
CPU
incl. 16
Registers
Emulation
2BP
JTAG
Interface
Spy-Bi-
Wire
RST/NMI
Brownout
Protection
Comp_A+
8 Channels
Watchdog
WDT+
15-Bit
Timer0_A3
3 CC
Registers
Timer1_A3
3 CC
Registers
USCI A0
UART/
LIN, IrDA,
SPI
USCI B0
SPI, I2C
NOTE: Port P3 is available on 28-pin and 32-pin devices only.
4
Copyright
©
2011, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
