MSP430FR573x
MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
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(1)
Table 55. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS/ SIGNALS
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x PJSEL1.x PJSEL0.x
(2)
PJ.0/TDO/TB0OUTH/SMCLK/CD6
0
PJ.0 (I/O)
I: 0; O: 1
0
0
(3)
TDO
X
X
X
TB0OUTH
SMCLK
CD6
0
0
1
1
X
1
0
X
1
0
X
(2)
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
PJ.3/TCK/CD9
1
2
3
PJ.1 (I/O)
TDI/TCLK
TB1OUTH
MCLK
I: 0; O: 1
(3) (4)
X
0
0
1
1
CD7
X
1
0
X
1
0
X
(2)
PJ.2 (I/O)
I: 0; O: 1
(3) (4)
TMS
X
TB2OUTH
ACLK
0
0
1
1
CD8
X
1
0
X
1
1
0
X
1
(2)
PJ.3 (I/O)
I: 0; O: 1
(3) (4)
TCK
X
X
CD9
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made by the SYS module or by the Spy-Bi-Wire four-wire
entry sequence. PJSEL1.x and PJSEL0.x have no effect in these cases.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
86
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