MSP430FR573x
MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
www.ti.com
Pad Logic
To XT1 XOUT
PJSEL0.4
XT1BYPASS
PJREN.5
0 0
0 1
1 0
1 1
PJDIR.5
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.5
DVSS
DVSS
DVSS
PJ.5/XOUT
PJSEL0.5
PJSEL1.5
PJIN.5
Bus
Keeper
EN
D
To modules
Table 56. Port PJ (PJ.4 and PJ.5) Pin Functions
(1)
CONTROL BITS/SIGNALS
PIN NAME (P7.x)
x
FUNCTION
XT1
BYPASS
PJDIR.x PJSEL1.5 PJSEL0.5 PJSEL1.4 PJSEL0.4
PJ.4/XIN
4
PJ.4 (I/O)
I: 0; O: 1
X
X
X
0
X
X
X
0
0
0
0
0
0
1
1
0
X
0
1
X
(2)
XIN crystal mode
XIN bypass mode
PJ.5 (I/O)
X
X
(2)
PJ.5/XOUT
5
I: 0; O: 1
XOUT crystal mode
X
X
X
X
X
0
0
1
1
0
1
(3)
(4)
PJ.5 (I/O)
I: 0; O: 1
(1) X = Don't care
(2) Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When XT1BYPASS = 0, PJ.4 and PJ.5 are
configured for crystal operation and PJSEL1.5 and PJSEL0.5 are do not care. When XT1BYPASS = 1, PJ.4 is configured for bypass
operation and PJ.5 is configured as general-purpose I/O.
(3) Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When XT1BYPASS = 0, PJ.4 and PJ.5 are
configured for crystal operation and PJSEL1.5 and PJSEL0.5 are do not care. When XT1BYPASS = 1, PJ.4 is configured for bypass
operation and PJ.5 is configured as general-purpose I/O.
(4) When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.
88
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated