MSP430FR573x
MSP430FR572x
SLAS639D – JULY 2011 – REVISED AUGUST 2012
Table 4. Terminal Functions (continued)
TERMINAL
NAME
NO.
RHA
RGE
DA
PW
YFF
I/O
(1)
DESCRIPTION
P2.5/TB0.0/UCA1TXD/
UCA1SIMO
17
N/A
19
15
N/A
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB0 CCR0 capture: CCI0A input, compare: Out0
Transmit data – eUSCI_A1 UART mode, Slave in, master out –
eUSCI_A1 SPI mode (not available on devices without UCSI_A1)
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on
devices without TB1)
Receive data – eUSCI_A1 UART mode, Slave out, master in –
eUSCI_A1 SPI mode (not available on devices without UCSI_A1)
Test mode pin – enable JTAG pins
Spy-Bi-Wire input clock
Reset input active low
Non-maskable interrupt input
Spy-Bi-Wire data input/output
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P2.6/TB1.0/UCA1RXD/
UCA1SOMI
18
N/A
20
16
N/A
I/O
TEST/SBWTCK
(3) (4)
19
11
21
17
D5
I
RST/NMI/SBWTDIO
(3) (4)
20
12
22
18
D4
I/O
P2.0/TB2.0/UCA0TXD/
UCA0SIMO/TB0CLK/ACLK
(4)
21
13
23
19
E5
I/O
TB2 CCR0 capture: CCI0A input, compare: Out0 (not available on
devices without TB2)
Transmit data – eUSCI_A0 UART mode, Slave in, master out –
eUSCI_A0 SPI mode
TB0 clock input
ACLK output
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB2 CCR1 capture: CCI1A input, compare: Out1 (not available on
devices without TB2)
Receive data – eUSCI_A0 UART mode, Slave out, master in –
eUSCI_A0 SPI mode
TB0 CCR0 capture: CCI0A input, compare: Out0
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB2 CCR2 capture: CCI2A input, compare: Out2 (not available on
devices without TB2)
Clock signal input – eUSCI_B0 SPI slave mode, Clock signal
output – eUSCI_B0 SPI master mode
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on
devices without TB1)
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
TB1 CCR1 capture: CCI1B input, compare: Out1 (not available on
devices without TB1)
TB2 clock input (not available on devices without TB2 or package
options PW, RGE)
SMCLK output (not available on package options PW, RGE)
P2.1/TB2.1/UCA0RXD/
UCA0SOMI/TB0.0
(5)
22
14
24
20
D3
I/O
P2.2/TB2.2/UCB0CLK/ TB1.0
23
15
25
21
E4
I/O
P3.4/TB1.1/TB2CLK/ SMCLK
24
N/A
26
N/A
N/A
I/O
(4)
(5)
16
See
and
for use with BSL and JTAG functions.
See
and
for use with BSL and JTAG functions.
Copyright © 2011–2012, Texas Instruments Incorporated
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