MSP430F673x
MSP430F672x
SLAS731A –DECEMBER 2011–REVISED APRIL 2012
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INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 and P1.1, Input/Output With Schmitt Trigger (MSP430F67xxIPZ and
MSP430F67xxIPN)
Pad Logic
to/from Reference
To ADC10_A
INCHx = y
P1REN.x
P1MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P1OUT.x
0
1
from Port Mapping
P1.0/PM_TA0.0/VeREF-/A2
P1.1/PM_TA0.1/VeREF+/A1
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
D
to Port Mapping
P1IRQ.x
P1IE.x
EN
Set
Q
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge
Select
Table 63. Port P1 (P1.0 and P1.1) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
CONTROL BITS/SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1MAPx
X
P1.0/PM_TA0.0/
VeREF-/A2
0
P1.0 (I/O)
I: 0; O: 1
0
1
1
1
0
1
1
1
TA0.CCI0A
TA0.TA0
VeREF-/A2(2)
0
default
default
= 31
1
X
P1.1/PM_TA0.1/
VeREF+/A1
1
P1.1 (I/O)
I: 0; O: 1
X
TA0.CCI1A
TA0.TA1
VeREF+/A1(2)
0
1
X
default
default
= 31
(1) X = Don't care
(2) Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver as well as the input Schmitt trigger.
82
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