MSP430F673x
MSP430F672x
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SLAS731A –DECEMBER 2011–REVISED APRIL 2012
Port P1, P1.6 and P1.7 (MSP430F67xxIPZ and MSP430F67xxIPN),
Port P2, P2.0 and P2.1 (MSP430F67xxIPZ Only) Input/Output With Schmitt Trigger
COM4 to COM7
from LCD_C
Pad Logic
PyREN.x
PyMAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
PyDIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
PyOUT.x
0
1
from Port Mapping
P1.6/PM_UCA0CLK/COM4
P1.7/PM_UCB0CLK/COM5
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7
PyDS.x
0: Low drive
1: High drive
PySEL.x
PyIN.x
Bus
Keeper
EN
D
to Port Mapping
PyIE.x
EN
PyIRQ.x
Q
PyIFG.x
Set
PySEL.x
PyIES.x
Interrupt
Edge
Select
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