MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
12-Bit DAC, Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DAC12IR = 0(1) (2)
VCC
MIN
TYP
MAX UNIT
AVCC AVCC
/ 3
+ 0.2
Reference input voltage
range
VeREF+
2.2 V, 3 V
V
AVCC
+ 0.2
DAC12IR = 1(3) (4)
AVCC
DAC12_0 IR = DAC12_1 IR = 0
DAC12_0 IR = 1, DAC12_1 IR = 0
DAC12_0 IR = 0, DAC12_1 IR = 1
20
MΩ
48
48
Ri(VREF+)
Ri(VeREF+)
,
Reference input resistance(5)
2.2 V, 3 V
kΩ
DAC12_0 IR = DAC12_1 IR = 1,
24
DAC12_0 SREFx = DAC12_1 SREFx(6)
(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
(2) The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
(4) The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
(5) This impedance depends on tradeoff in power savings. Current devices have 48 kΩ for each channel when divide is enabled. Can be
increased if performance can be maintained.
(6) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-Bit DAC, Dynamic Specifications
VREF = VCC, DAC12IR = 1 (see Figure 19 and Figure 20), over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DAC12AMPx = 0 → {2, 3, 4}
VCC
MIN
TYP
60
MAX UNIT
120
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB(1)
(see Figure 19)
tON
DAC12 on time
DAC12AMPx = 0 → {5, 6}
DAC12AMPx = 0 → 7
DAC12AMPx = 2
2.2 V, 3 V
15
30
12
µs
µs
µs
6
100
40
200
80
DAC12_xDAT =
tS(FS)
tS(C-C)
SR
Settling time, full scale
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
DAC12AMPx = 2
2.2 V, 3 V
2.2 V, 3 V
80h → F7Fh → 80h
15
30
5
DAC12_xDAT =
Settling time, code to
code
3F8h → 408h → 3F8h,
BF8h → C08h → BF8h
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
DAC12AMPx = 2
2
1
0.05
0.35
1.50
0.35
1.10
5.20
DAC12_xDAT =
Slew rate
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
2.2 V, 3 V
2.2 V, 3 V
V/µs
nV-s
80h → F7Fh → 80h(2)
DAC12_xDAT =
Glitch energy
DAC12AMPx = 7
35
800h → 7FFh → 800h
(1) RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 19.
(2) Slew rate applies to output voltage steps ≥ 200 mV.
Conversion 1
Conversion 2
1/2 LꢀS
Conversion 3
VOUT
DAC Output
RLoad = 3 kW
ILoad
Glitch
Energy
AVCC
2
1/2 LꢀS
CLoad = 100 pF
RO/P(DAC12.x)
tsettleLH
tsettleHL
Figure 19. Settling Time and Glitch Energy Testing
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77
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