MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
USB-PLL (USB Phase-Locked Loop)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Operating supply current
PLL frequency
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
IPLL
7
mA
MHz
MHz
ms
fPLL
48
fUPD
tLOCK
tJitter
PLL reference frequency
PLL lock time
1.5
3
2
PLL jitter
1000
ps
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX UNIT
DVCC(PGM/ERASE) Program and erase supply voltage
1.8
3.6
5
V
IPGM
Average supply current from DVCC during program
3
mA
mA
IERASE
Average supply current from DVCC during erase
2.5
Average supply current from DVCC during mass erase or bank
erase
IMERASE, IBANK
tCPT
2
mA
(1)
Cumulative program time
See
16
ms
cycles
years
µs
Program and erase endurance
Data retention duration
104
100
64
105
tRetention
tWord
TJ = 25°C
(2)
Word or byte program time
Block program time for first byte or word
See
85
65
(2)
tBlock, 0
See
49
µs
Block program time for each additional byte or word, except for last
byte or word
(2)
tBlock, 1–(N–1)
tBlock, N
See
37
55
23
49
73
32
µs
µs
(2)
Block program time for last byte or word
See
Erase time for segment, mass erase, and bank erase when
available
(2)
tSeg Erase
See
ms
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1)
fMCLK,MGR
0
1
MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
(2) These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
0
20 MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
0.025
15
µs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge)(1)
tSBW, En
tSBW,Rst
2.2 V, 3 V
1
µs
Spy-Bi-Wire return to normal operation time
TCK input frequency (4-wire JTAG)(2)
Internal pulldown resistance on TEST
15
0
100
5
µs
2.2 V
3 V
MHz
fTCK
0
10 MHz
80 kΩ
Rinternal
2.2 V, 3 V
45
60
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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