MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
12-Bit DAC, Linearity Specifications (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V
±21(2)
Without calibration(1) (3)
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
3 V
2.2 V
±21
mV
EO
Offset voltage
VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1
±1.5(2)
With calibration(1) (3)
With calibration
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
3 V
±1.5
Offset error
temperature
coefficient(1)
dE(O)/dT
2.2 V, 3 V
±10
10
µV/°C
VeREF+ = 1.5 V
VeREF+ = 2.5 V
2.2 V
3 V
±2.5
EG
Gain error
%FSR
±2.5
ppm
of
FSR/
°C
Gain temperature
coefficient(1)
dE(G)/dT
2.2 V, 3 V
2.2 V, 3 V
DAC12AMPx = 2
165
Time for offset
calibration(4)
tOffset_Cal
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
66
ms
16.5
(3) The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
(4) The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx =
{0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may effect
accuracy and is not recommended.
DAC VOUT
DAC Output
VR+
RLoad = ¥
Ideal transfer
function
AVCC
2
Offset Error
Positive
Gain Error
CLoad = 100 pF
Negative
DAC Code
Figure 17. Linearity Test Load Conditions and Gain/Offset Definition
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