MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 11 and )
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
SMCLK, ACLK,
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ± 10%
PMMCOREV = 0
1.8 V
3 V
55
38
30
25
0
ns
ns
ns
tSU,MI
SOMI input data setup time
SOMI input data hold time
2.4 V
3 V
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
1.8 V
3 V
0
tHD,MI
2.4 V
3 V
0
ns
0
UCLK edge to SIMO valid,
CL = 20 pF,
PMMCOREV = 0
1.8 V
20
ns
3 V
18
tVALID,MO
SIMO output data valid time(2)
SIMO output data hold time(3)
2.4 V
3 V
16
ns
15
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3
1.8 V
3 V
-10
-8
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 3
ns
ns
tHD,MO
2.4 V
3 V
-10
-8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 11 and .
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 11 and .
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 11. SPI Master Mode, CKPH = 0
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