LMH0324
ZHCSIC8B –APRIL 2016–REVISED JUNE 2018
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 General Guidance for SMPTE Applications
SMPTE specifies the requirements for the Serial Digital Interface to transport digital video over coaxial cables.
One of the requirements is meeting return loss, which specifies how closely the port resembles 75-Ω impedance
across a specified frequency band. The SMPTE specifications also defines the use of AC coupling capacitors for
transporting uncompressed serial data streams with heavy low frequency content. The use of 4.7-μF AC coupling
capacitors is recommended to avoid low frequency DC wander. Refer to 表 8 for design requirements.
8.2 Typical Application
The LMH0324 is a low-power SDI equalizer that supports SDI data rates from 125 Mbps to 2.97 Gbps. 图 16
shows a typical implementation of the LMH0324 as a SDI adaptive cable equalizer. Signal attenuated by a long
coax cable is applied to the LMH0324 at the BNC port. Equalized data is output at OUT0± and OUT1± to a
downstream video processor.
2.5 V
0.1 µF
0.1 µF
1 µF
10 µF
75 ꢀ BNC
4.7 µF
RSV_L
VDDIO
VIN
OUT0+
75 Ω board trace
75 Ω board trace
IN0+
IN0-
RX+
RX-
100 Ω coupled trace
4.7 µF
OUT0-
VDD_LDO
EP
VSS
VSS
VSS
75 Ω
1 µF
0.1 µF
FPGA/Video
Processor
LMH0324
RSV1
RSV2
OUT1+
OUT1-
RX+
RX-
100-Ω coupled trace
4.7 µF
MODE_SEL = Float Enables SPI Interface
1 kΩ
220 Ω
VDDIO
图 16. LMH0324 SPI Mode Connection Diagram
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