GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP
SLWS137A
frequency and “Clock Rate” is the chip’s clock rate. The frequency register is double buffered so that
frequency changes can be made synchronous to external sync signals.
The upper 16 bits of the current phase increment is monitored by the phase increment register. The
register tracks the current phase increment when the “hold” control is low and holds the last value when
“hold” is high. The user may wish to monitor the phase increment in order to reinitialize the PLL after a loss
of signal, or to determine when carrier lock has been achieved.
2.9
NCO
The PLL circuit generates a phase increment word which is used by the NCO to generate a
sine/cosine sequence at the desired tuning frequency. The NCO circuit accumulates the phase and uses
the upper 13 bits of the 32 bit accumulator to lookup 12 bit sines and cosines. A block diagram of the NCO
circuit is shown in Figure 6.
NCO Sync
Dither
Sync
12 Bits
12 Bits
ACOS
ASIN
17 Bits
13 Bits
PHASE
INCREMENT
TRIG
TABLE
CIN
32 BIT PHASE ACCUMULATOR
12 Bits
12 Bits
BCOS
BSIN
13 Bits
17 Bits
TRIG
TABLE
DIVIDE BY 2
Clear
Negate Sine
High Speed
Mode
Figure 6. NCO CIRCUIT
The accumulator output plus one half the phase increment is used in the high speed mode1 to look
up the BCOS and BSIN values. This generates the proper “odd time” sine/cosine values needed in the high
speed mode. The tuning range in the high speed mode is limited to +/- FIN/4, where FIN is thehigh speed
input data rate. To tune to frequencies above FIN/4, the user must negate the odd-time output samples (both
I and Q). This mixes the output down by FIN/2. For example, to mix down the frequency 0.3IN, the user
should set the tuning frequency to +0.2FIN, and then negate the odd-time output data to give a final tuning
of (0.2FIN - 0.5FIN) = -0.3FIN.
The dither circuit adds a random value to the upper 17 bits of the accumulator output. The random
number sequence is initialized to zero by the dither sync input. The dithering can be turned off by forcing
the sync to be active. The BSIN output is negated if the high speed mode is not enabled.
2.10
SNAPSHOT RAM
The snapshot RAM is used to store blocks of 64 mixer and NCO outputs. The mixer outputs are the
SI and SQ outputs shown in Figure 3. The NCO samples are the ACOS and ASIN values shown in Figure
3. The NCO samples are delayed to match the pipeline delay from the XI and XQ inputs to the SI and SQ
1. The high speed mode is the double rate real input mode, see Section 2.4
Texas Instruments Incorporated
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