GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP
2.13 POWER DOWN MODES
SLWS137A
The chip has a power down and clock loss detect circuit. This circuit detects if the clock is absent
long enough to cause dynamic storage nodes to lose state. If clock loss is detected, an internal reset state
is entered to force the dynamic nodes to become static. The control registers are not reset and will retain
their values, but any data values within the chip will be lost. When the clock returns to normal the chip will
automatically return to normal. In the reset state the chip consumes only a small amount of standby power.
The user can select whether this circuit is in the automatic clock-loss detect mode, is always on (power down
mode), or is disabled (the clock reset never kicks in) using the POWER_DOWN control bits in address 1.
NOTE: The chip is in the power down mode when power is applied, and must be enabled by setting
the power down mode to "2" in register 1.
Texas Instruments Incorporated
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