GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP
SLWS137A
2.5
MIXER
The mixer multiplies the pairs of samples from the input format circuit by sines and cosines and
outputs the results to the output format and the symbol offset circuits. A block diagram of the mixer circuit
is shown in Figure 3.
Round Adder
Enable Clear
Add
2X Gain
DC_I_IN
12 Bits
XI
(even)
12 Bits
Ieven
Qodd
Qeven
From
ACOS 12 Bits
Input Format
Circuit
12 Bits
12 Bits
DC_I_OUT
12 Bits
SI
DC_Q_IN
12 Bits
XQ
(odd)
Symbol
Data To
Symbol Offset
Circuit
12 Bits
BSIN
12 Bits
12 Bits
ASIN
12 Bits
12 Bits
DC_Q_OUT
12 Bits
SQ
Iodd
BCOS 12 Bits
Figure 3. MIXER
The ACOS, BCOS, ASIN and BSIN values are generated by the NCO circuit. In the complex mode
BCOS will equal ACOS and BSIN will equal minus ASIN. In the high speed mode the ASIN and ACOS
values are the even time sine/cosine pairs and the BCOS and BSIN values are the odd time pairs. The lower
11 bits of the 23 bit multiplier products are either rounded off or truncated depending upon the state of the
round enable control. The rounding is performed using the “round to even” technique1. The 12 bit products
are passed to the output format circuit.
The adders sum the individual products to generate complex products. The adder outputs are
saturated to 12 bits if the add causes overflow. The adder outputs pass through a gain circuit and then to
the symbol offset circuit. The gain circuit, if it is enabled, doubles the data values. The gain outputs are
saturated to plus or minus full scale if the gain causes overflow2. The adder clear control allows the Ieven
and Qeven mixer outputs, instead of the complex products, to be passed to the symbol gain circuit. This
permits the user to capture the high speed mode’s even outputs in the snapshot RAM, or to use them in the
phase error lookup circuit.
DC components before or after the mixer can be removed by adjusting the DC_I_IN, DC_Q_IN,
DC_I_OUT and the DC_Q_OUT values. These values are added to the input and output data as shown in
1. When the fraction to be rounded is exactly 1/2, the round to even technique rounds up when the integer portion is odd and rounds
down when it is even. This removes any DC bias in the rounding.
2. The input samples of QAM signals have an extra sign bit before the carrier is removed. The extra sign bit is needed because the
square QAM constellation is spinning. Once carrier has been removed the extra sign bit can be removed by the gain circuit. This
increases the resolution of the phase error RAM and simplifies the symbol mapping.
Texas Instruments Incorporated
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