GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP
SLWS137A
2.3
CLOCK GENERATOR
The clock generator generates the internal clocks from the clock input (CK). Two clock enable
inputs (CKENA and CKENB) are used to enable or disable the clock. Both enables must be low for internal
clocks to be generated. The enables are clocked into the chip and are used to enable or disable the following
clock edge. The enables are designed to be used with the data valid strobes from the GC3021A digital
resampler and GC2011Adigital filter chips.
2.4
INPUT FORMAT
The input format circuit accepts complex data at the clock rate of the chip, or real data at twice the
clock rate of the chip. The input format circuit outputs pairs of samples to the mixer circuit where the pair is
either a complex data pair, or an even and odd time sample pair. A block diagram of the input circuit is
shown in Figure 2.
I
Q
12 Bits
12 Bits
12 Bits
XI
COMPLEX
DATA
Data
To
Mixer
DATA
MUX
or
EVEN/ODD
12 Bits
XQ
PAIR
Diagnostic
Ramp
12 Bits
Mode
Select
Figure 2. INPUT FORMAT CIRCUIT
The even/odd data inputs share pins with the I/Q complex data inputs. The I input pins are used as
the even time inputs and the Q pins are used as the odd time inputs. The even samples are assumed to
preceed the odd time samples. I.E., (X0, X2, X4, ...) are the even time samples, (X1, X3, X5,..) are the odd
time samples.
Texas Instruments Incorporated
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