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DP83848IVVX 参数 Datasheet PDF下载

DP83848IVVX图片预览
型号: DP83848IVVX
PDF下载: 下载PDF文件 查看货源
内容描述: DP83848I PHYTER工业温度单端口10/100 Mb / s以太网物理层收发器 [DP83848I PHYTER Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver]
分类和应用: 以太网局域网(LAN)标准
文件页数/大小: 86 页 / 788 K
品牌: TI [ TEXAS INSTRUMENTS ]
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7.2.2 MII Interrupt Control Register (MICR)  
This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy  
Detect State Change, Link State Change, Speed Status Change, Duplex Status Change, Auto-Negotiation Complete or  
any of the counters becoming half-full. The individual interrupt events must be enabled by setting bits in the MII Inter-  
rupt Status and Event Control Register (MISR).  
Table 22. MII Interrupt Control Register (MICR), address 0x11  
Bit  
15:3  
2
Bit Name  
Reserved  
TINT  
Default  
0, RO  
Description  
Reserved: Write ignored, Read as 0  
Test Interrupt:  
0, RW  
Forces the PHY to generate an interrupt to facilitate interrupt test-  
ing. Interrupts will continue to be generated as long as this bit re-  
mains set.  
1 = Generate an interrupt  
0 = Do not generate interrupt  
Interrupt Enable:  
1
0
INTEN  
0, RW  
0, RW  
Enable interrupt dependent on the event enables in the MISR reg-  
ister.  
1 = Enable event based interrupts  
0 = Disable event based interrupts  
Interrupt Output Enable:  
INT_OE  
Enable interrupt events to signal via the PWR_DOWN/INT pin by  
configuring the PWR_DOWN/INT pin as an output.  
1 = PWR_DOWN/INT is an Interrupt Output  
0 = PWR_DOWN/INT is a Power Down Input  
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