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DP83848IVVX 参数 Datasheet PDF下载

DP83848IVVX图片预览
型号: DP83848IVVX
PDF下载: 下载PDF文件 查看货源
内容描述: DP83848I PHYTER工业温度单端口10/100 Mb / s以太网物理层收发器 [DP83848I PHYTER Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver]
分类和应用: 以太网局域网(LAN)标准
文件页数/大小: 86 页 / 788 K
品牌: TI [ TEXAS INSTRUMENTS ]
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7.2 Extended Registers  
7.2.1 PHY Status Register (PHYSTS)  
This register provides a single location within the register set for quick access to commonly accessed information.  
Table 21. PHY Status Register (PHYSTS), address 0x10  
Bit  
15  
14  
Bit Name  
RESERVED  
MDI-X mode  
Default  
0, RO  
0, RO  
Description  
RESERVED: Write ignored, read as 0.  
MDI-X mode as reported by the Auto-Negotiation logic:  
This bit will be affected by the settings of the MDIX_EN and  
FORCE_MDIX bits in the PHYCR register. When MDIX is en-  
abled, but not forced, this bit will update dynamically as the  
Auto-MDIX algorithm swaps between MDI and MDI-X configu-  
rations.  
1 = MDI pairs swapped  
(Receive on TPTD pair, Transmit on TPRD pair)  
0 = MDI pairs normal  
(Receive on TRD pair, Transmit on TPTD pair)  
Receive Error Latch:  
13  
12  
Receive Error Latch  
Polarity Status  
0, RO/LH  
This bit will be cleared upon a read of the RECR register.  
1 = Receive error event has occurred since last read of RXERCNT  
(address 0x15, Page 0).  
0 = No receive error event has occurred.  
0, RO  
Polarity Status:  
This bit is a duplication of bit 4 in the 10BTSCR register. This bit will  
be cleared upon a read of the 10BTSCR register, but not upon a  
read of the PHYSTS register.  
1 = Inverted Polarity detected.  
0 = Correct Polarity detected.  
11  
False Carrier Sense  
Latch  
0, RO/LH  
False Carrier Sense Latch:  
This bit will be cleared upon a read of the FCSR register.  
1 = False Carrier event has occurred since last read of FCSCR (ad-  
dress 0x14).  
0 = No False Carrier event has occurred.  
100Base-TX unconditional Signal Detect from PMD.  
100Base-TX Descrambler Lock from PMD.  
Link Code Word Page Received:  
10  
9
Signal Detect  
Descrambler Lock  
Page Received  
0, RO/LL  
0, RO/LL  
0, RO  
8
This is a duplicate of the Page Received bit in the ANER register,  
but this bit will not be cleared upon a read of the PHYSTS register.  
1 = A new Link Code Word Page has been received. Cleared on  
read of the ANER (address 0x06, bit 1).  
0 = Link Code Word Page has not been received.  
7
6
MII Interrupt  
0, RO  
0, RO  
MII Interrupt Pending:  
1 = Indicates that an internal interrupt is pending. Interrupt source  
can be determined by reading the MISR Register (0x12h). Reading  
the MISR will clear the Interrupt.  
0= No interrupt pending.  
Remote Fault  
Remote Fault:  
1 = Remote Fault condition detected (cleared on read of BMSR (ad-  
dress 01h) register or by reset). Fault criteria: notification from Link  
Partner of Remote Fault via Auto-Negotiation.  
0 = No remote fault condition detected.  
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