8.0 Electrical Specifications
8.3 CLOCK TIMING
8.3.1 Clock Reference and Clock Generation Timing
Parameter
Description
Notes
Min
Typ
30
5
Max
Units
ns
T1
T2
T3
T4
OSCIN to CLK25M Delay OSCIN = 50 MHz
0
40
CLK25M Rise Time
CLK25M Fall Time
10% to 90%
90% to 10%
ns
5
ns
OSCIN to TX_CLK Delay 10 Mb/s Operation (MII
Nibble Mode)
10
ns
T4a
OSCIN to TX_CLK Delay 10 Mb/s Operation (MII
Serial Mode)
10
ns
T5
T6
REFIN to TX_CLK Delay 100 Mb/s Operation
-3.0
35
+3.0
65
ns
%
TX_CLK Duty Cycle
10 Mb/s Nibble (2.5 MHz),
10 Mb/s Serial (10 MHz)
100 Mb/s Nibble (25 MHz)
OSCIN
T1
T2
T1
T3
CLK25M
REFIN
T5
T4
T6
TX_CLK
Version A
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