7.0 Hardware User Information (Continued)
Description:
When the part receives a JAM signal that has a
combination of 5 MHz and 10 MHz signals, CRS will glitch.
CRS behaves normally when a 101010... JAM pattern is
received. All repeaters and most MACs send out 101010...
JAM signals, but there are a few MACs that will send out
pseudo-random 5/10 MHz data.
The DP83840A when in 10 Mb/s Repeater Mode does not
conform to 802.3 IEEE specification for Carrier Sense
(CRS). The specification states that CRS becomes active
whenever the receive input becomes active and in-active
when there is no activity. The DP83840A uses its’ internal
Phase Lock Loop (PLL) to gate CRS. This causes CRS to Solution/Workaround:
glitch when the PLL switches from Receive mode to
Putting the part into Full-Duplex mode eliminates the CRS
Transmit mode and when the PLL switches from Transmit
to Receive mode. The switching of modes is what occurs
during collisions.
glitching problem. However, when the part is in Full-Duplex
mode the COL pin (pin 65) will not indicate if collisions
have occurred.
Symptoms:
When the part is receiving a packet and then TX_EN is
asserted, CRS will glitch twice, once following the rising
edge of TX_EN and once following the end of RXI+/-. This
is illustrated in Figure 27.
RXI +/-
CRS
TX_EN
FIGURE 27. CRS Glitching
Version A
National Semiconductor
69
TI [ TEXAS INSTRUMENTS ]
