8.0 Electrical Specifications (Continued)
8.5.3 100 Mb/s Transmit Packet Timing
Parameter
Description
Notes
Min
Typ Max Units
T1
TX_CLK to TD+/- Latency
100 Mb/s Translational mode (Normal)
100 Mb/s Transparent mode (BP_4B5B)
100 Mb/s Phaser mode (BP_ALIGN)
3.0
3.0
3.0
bits
bits
bits
Note: Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN
to the first bit of the “j” code group as output from the TD+/- pins. 1 bit time = 10ns in 100 Mb/s mode
TX_CLK
TX_EN
TXD
T1
TD+/-
IDLE
(J/K)
DATA
8.5.4 100 Mb/s Transmit Packet Timing
Parameter
Description
Notes
Min
Typ Max Units
T1
TX_CLK to TD+/- deassertion 100 Mb/s Translational mode (Normal)
30
30
30
ns
ns
ns
100 Mb/s Transparent mode (BP_4B5B)
100 Mb/s Phaser mode (BP_ALIGN)
Note: De-assertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the de-assertion of TX_EN
to the first bit of the “T” code group as output from the TD+/- pins. 1 bit time = 10ns in 100 Mb/s mode
TX_CLK
TXD
TX_EN
T1
TD+/-
DATA
(T/R)
IDLE
Version A
77
TI [ TEXAS INSTRUMENTS ]
