DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL
RESET
REL.
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
BALL
RESET
STATE [9]
MODE
[6]
BUFFER
TYPE [13]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [7] DSIS [8]
POWER [11]
HYS [12]
STATE [10]
H2
VOUT[1]_R_CR[4]
VOUT[1]_R_CR[4]
PINCNTL222 /
0x4814 0B74
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x01
O
PIN
PIN
PIN
1
L
L
L
L
L
DVDD
DVDD
DVDD
DVDD
EMAC[1]_MTXD[3]
VIN[1]A_D[15]
SPI[3]_SCS[1]
GP3[14]
0x02
0x04
0x20
0x80
0x01
0x02
0x04
0x20
0x80
0x01
0x02
0x04
0x20
0x80
0x01
0x02
0x04
0x20
0x80
0x01
0x02
0x04
0x80
0x01
0x02
0x04
0x80
0x01
0x02
0x04
0x08
0x10
0x80
NA
O
I
I/O
I/O
O
PIN
PIN
PIN
PIN
1
M11
VOUT[1]_R_CR[5]
VOUT[1]_R_CR[6]
VOUT[1]_R_CR[7]
VOUT[1]_R_CR[5]
EMAC[1]_MTXD[4]
VIN[1]A_D[16]
SPI[3]_SCLK
GP3[15]
PINCNTL223 /
0x4814 0B78
L
L
L
O
I
I/O
I/O
O
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
0
L12
VOUT[1]_R_CR[6]
EMAC[1]_MTXD[5]
VIN[1]A_D[17]
SPI[3]_D[1]
PINCNTL224 /
0x4814 0B7C
O
I
I/O
I/O
O
GP3[16]
M10
VOUT[1]_R_CR[7]
EMAC[1]_MTXD[6]
VIN[1]A_D[18]
SPI[3]_D[0]
PINCNTL225 /
0x4814 0B80
O
I
I/O
I/O
O
GP3[17]
J2
K2
F5
VOUT[1]_R_CR[8]
VOUT[1]_R_CR[9]
VOUT[1]_VSYNC
VOUT[1]_R_CR[8]
EMAC[1]_MTXD[7]
VIN[1]A_D[19]
GP3[18]
PINCNTL226 /
0x4814 0B84
0x0004 0000
0x0004 0000
0x0004 0000
L
L
L
L
L
L
DVDD
DVDD
DVDD
O
I
I/O
O
VOUT[1]_R_CR[9]
EMAC[1]_MTXEN
VIN[1]A_D[20]
GP3[19]
PINCNTL227 /
0x4814 0B88
O
I
I/O
O
VOUT[1]_VSYNC
EMAC[1]_MCRS
VIN[1]A_FLD
VIN[1]A_DE
PINCNTL206 /
0x4814 0B34
I
I
0
I
0
SPI[3]_D[0]
I/O
I/O
PWR
PIN
PIN
NA
GP2[30]
AL18
VREFSSTL_DDR[0]
VREFSSTL_DDR[0]
NA /
NA
NA
NA
NA
DVDD_DDR[0]
Copyright © 2013, Texas Instruments Incorporated
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