DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
www.ti.com
• General-Purpose Memory Controller (GPMC)
• Four Inter-Integrated Circuit (I2C Bus™) Ports
• Two Multichannel Audio Serial Ports (McASP)
– Six Serializer Transmit and Receive Ports
– Two Serializer Transmit and Receive Ports
– DIT-Capable For S/PDIF (All Ports)
• Four Audio Tracking Logic (ATL) Modules
• Real-Time Clock (RTC)
– One-Time or Periodic Interrupt Generation
• Up to 125 General-Purpose I/O (GPIO) Pins
– 8- or 16-Bit Multiplexed Address and Data
Bus
– 512MB of Total Address Space Divided
Among up to 8 Chip Selects
– Glueless Interface to NOR Flash, NAND
Flash (BCH/Hamming Error Code Detection),
SRAM and Pseudo-SRAM
– Error Locator Module (ELM) Outside of
GPMC to Provide up to 16-Bit or 512-Byte
Hardware ECC for NAND
• One Spin Lock Module with up to 128 Hardware
Semaphores
– Flexible Asynchronous Protocol Control for
Interface to FPGA, CPLD, ASICs, and More
• One Mailbox Module with 12 Mailboxes
• On-Chip ARM ROM Bootloader (RBL)
• Power, Reset, and Clock Management
– SmartReflex™ Technology (Level 2b)
– Multiple Independent Core Power Domains
– Multiple Independent Core Voltage Domains
• Enhanced Direct Memory Access (EDMA)
Controller
– Four Transfer Controllers
– 64 Independent DMA Channels
– 8 QDMA Channels
– Support for Multiple Operating Points per
Voltage Domain
– Clock Enable and Disable Control for
Subsystems and Peripherals
• Ethernet Switch with Dual 10-, 100-, or
1000-Mbps External Interfaces (EMAC
Software)
– IEEE 802.3 Compliant (3.3-V I/O Only)
• 32KB of Embedded Trace Buffer™ (ETB™) and
5-pin Trace Interface for Debug
– MII/RMII/GMII/RGMII Media Independent
Interfaces
• IEEE 1149.1 (JTAG) Compatible
– Management Data I/O (MDIO) Module
– Reset Isolation
– IEEE 1588 Time-Stamping and Industrial
Ethernet Protocols
• 609-Pin Pb-Free BGA Package (AAR Suffix),
0.8-mm Effective Pitch with Via Channel
Technology to Reduce PCB Cost (0.5-mm Ball
Spacing)
• 45-nm CMOS Technology
• 1.8- and 3.3-V Dual Voltage Buffers for General
I/O
• Dual USB 2.0 Ports with Integrated PHYs
– USB2.0 High- and Full-Speed Clients
– USB2.0 High-, Full-, and Low-Speed Hosts
– Supports End Points 0-15
• One PCI Express 2.0 Port with Integrated PHY
– Supported on
•
•
All DM385 Devices
DM388 Devices with PCIe Enabled
– Single Port with 1 Lane at 5.0 GT/s
– Configurable as Root Complex or Endpoint
• Eight 32-Bit General-Purpose Timers
(Timer1–8)
• One System Watchdog Timer (WDT0)
• Three Configurable UART/IrDA/CIR Modules
– UART0 with Modem Control Signals
– Supports up to 3.6864 Mbps
– SIR, MIR, FIR (4.0 MBAUD), and CIR
• Four Serial Peripheral Interfaces (SPIs) (up to
48 MHz)
– Each with Four Chip Selects
• Three MMC/SD/SDIO Serial Interfaces (up to
48 MHz)
– Supporting up to 1-, 4-, or 8-Bit Modes
2
High-Performance System-on-Chip (SoC)
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