DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
Software initiates a Software Global Cold Reset by writing a "1" to the RST_GLOBAL_COLD_SW bit in
the PRM_RSTCTRL register in the PRCM.
For more detailed information on the PRM_RSTCTRL register, see the PRCM Registers section of the
Power, Reset, and Clock Management (PRCM) Module chapter in the device-specific Technical
Reference Manual.
7.3.7 Software Global Warm Reset
A Software Global Warm Reset is initiated under software control. It has the same effect and requirements
as a External Warm Reset (RESET pin), with the following exceptions:
•
•
BTMODE[15:0] pins are not re-latched
RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the
BTMODE[11] pin.
Software initiates a Software Global Warm Reset by writing a "1" to the RST_GLOBAL_WARM_SW bit in
the PRM_RSTCTRL register in the PRCM.
For more detailed information on the PRM_RSTCTRL register, see the PRCM Registers section of the
Power, Reset, and Clock Management (PRCM) Module chapter in the device-specific Technical
Reference Manual.
7.3.8 Test Reset (TRST pin)
A Test Reset is activated by the emulator asserting the TRST pin. The only effect a Test Reset has is to
reset the Test and Emulation Logic.
7.3.9 Local Reset
The Local Reset for various Modules within the device is controlled by programming the PRCM and/or the
Peripheral Module’s internal registers. Only the associated Module is reset when a Local Reset is
asserted, leaving the rest of the device unaffected.
For more details on Peripheral Local Resets, see the Reset Management section of the Power, Reset,
and Clock Management (PRCM) Module chapter in the device-specific Technical Reference Manual.
7.3.10 Reset Priority
If any of the above reset sources occur simultaneously, the device only processes the highest-priority
reset request. The reset request priorities, from high-to-low, are as follows:
1. Power-on Reset (POR)
2. Test Reset (TRST)
3. External Warm Reset (RESET pin)
4. Emulation Warm Resets
5. Watchdog Reset
6. Software Global Cold/Warm Resets
7.3.11 Reset Status Register
The Reset Status Register (PRM_RSTST) contains information about the last reset that occurred in the
system. For more information on this register, see the Power, Reset, and Clock Management (PRCM)
Module chapter in the device-specific Technical Reference Manual.
7.3.12 PCIE Reset Isolation
The device supports reset isolation for the PCI Express (PCIE) module. This means that the PCI Express
Subsystem can be reset without resetting the rest of the device.
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Power, Reset, Clocking, and Interrupts
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