DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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POR
1.8 V Supplies
(DVDD, DVDD_x, VDDA_x_1P8,
VDDA_1P8)
1.35 V/1.5 V/1.8 V DVDD_DDR[0]
3.3 V Supplies
(DVDD, DVDD_x, VDDA_x_3P3)
CVDD
CVDD_x
2
1
3
4
Both 1.8 V and DVDD_DDR[x] supplies must be powered up and stable prior to starting the ramp of the 3.3 V
supplies.
CVDD powered-up coincidently or prior to CVDD_ARM and CVDD_HDVICP supplies.
Figure 7-1. Power-Up Sequence
7.2.8.2 Power-Down Sequence
For proper device operation, the following power-down sequence in Table 7-6, Figure 7-2, Figure 7-3, and
Figure 7-4 must be followed.
Table 7-6. Power-Down Sequence Ramping Values
NO.
5
DESCRIPTION
MIN
MAX
UNIT
ms
CVDD, CVDD_x variable supplies to 1.8 V supplies
1.35-/1.5-/1.8-V DVDD_DDR[x] supplies to 1.8 V supplies
3.3 V supplies to 1.8 V supplies
0
6
0
(1)
ms
(1)
(2)
7
ms
(2)
8
CVDD_x supplies to CVDD supply
ms
(1) The 3.3 V supplies must never be more than 2 V above the 1.8 V supplies (see Figure 7-3).
(2) The CVDD supply must be powered down coincidentally or after CVDD_ARM and CVDD_HDVICP supplies (see Figure 7-4).
134
Power, Reset, Clocking, and Interrupts
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