DAC8571
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SLAS373A–DECEMBER 2002–REVISED JULY 2003
TIMING CHARACTERISTICS (continued)
VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; all specifications -40°C to 105°C (unless otherwise noted)
SYMBOL
PARAMETER
TEST CONDITIONS
Standard mode
MIN
20 + 0.1CB
20 + 0.1CB
10
TYP
MAX
1000
300
80
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
pF
ns
ns
Rise time of SCL signal after a
repeated START condition, and
after an acknowledge BIT
Fast mode
tRCL1
High-speed mode, CB - 100pF max
High-speed mode, CB - 400pF max
Standard mode
20
1600
300
300
40
20 + 0.1CB
20 + 0.1CB
10
Fast mode
tFCL
Fall time of SCL signal
Rise time of SDA signal
High-speed mode, CB - 100pF max
High-speed mode, CB - 400pF max
Standard mode
20
80
20 + 0.1CB
20 + 0.1CB
10
1000
300
80
Fast mode
tRCA
High-speed mode, CB - 100pF max
High-speed mode, CB - 400pF max
Standard mode
20
160
300
300
80
20 + 0.1CB
20 + 0.1CB
10
Fast mode
tFDA
Fall time of SDA signal
High-speed mode, CB - 100pF max
High-speed mode, CB - 400pF max
Standard mode
20
160
4.0
tSU; tSTO
Setup time for STOP condition
Fast mode
600
High-speed mode
160
CB
tSP
Capacitive load for SDA and SCL
Pulse width of spike suppressed
400
50
Fast mode
High-speed mode
Standard mode
Fast mode
10
Noise margin at the HIGH level for
each connected device (including
hysteresis)
VNH
0.2VDO
0.1VDO
V
V
High-speed mode
Standard mode
Fast mode
Noise margin at the LOW level for
each connected device (including
hysteresis)
VNL
High-speed mode
5
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