CC1110Fx / CC1111Fx
Read/write to the control and status register
is done by the CPU, while read/write the
output/input registers is intended for use
together with direct memory access (DMA).
block at a time, except for the last block.
Before the last block is loaded, the mode
must be changed to CBC. The last block is
then downloaded and the block uploaded will
be the MAC value. CBC-MAC decryption is
similar to encryption. The message MAC
uploaded must be compared with the MAC
to be verified.
When using DMA, one channel is used for
input data and one for output data. The DMA
channels must be initialized before a start
command is written to the ENCCS. Writing a
start command generates a DMA trigger and
the transfer is started. After each block is
processed, the interrupt flag, S0CON.ENCIF,
is asserted, and an interrupt request
generated if IEN0.ENCIE is set to 1. The
interrupt is used to issue a new start
command to the ENCCS.
12.12.6 AES Interrupts
The AES interrupt flag, S0CON.ENCIF, is
asserted when encryption or decryption of a
block is completed. An interrupt request is
generated if IEN0.ENCIEis set to 1
12.12.7 AES DMA Triggers
12.12.5 Modes of Operation
There are two DMA triggers associated with
the AES coprocessor. These are ENC_DW,
which is active when input data needs to be
downloaded to the ENCDI register, and
ENC_UP, which is active when output data
needs to be uploaded from the ENCDO
register.
ECB and CBC modes are performed as
described in Section 12.12.1
When using CFB, OFB, and CTR mode, the
128 bits blocks are divided into four 32 bit
blocks. 32 bits are loaded into the AES
coprocessor and the resulting 32 bits are
read out. This continues until all 128 bits
have been encrypted. The only time one has
to consider this is if data is loaded/read
directly using the CPU. When using DMA,
this is handled automatically by the DMA
triggers generated by the AES coprocessor,
thus DMA is preferred.
The ENCDI and ENCDO registers should be
set as destination and source locations for
DMA channels used to transfer data to or
from the AES coprocessor.
12.12.8 AES Registers
Both encryption and decryption are
performed similarly.
The AES coprocessor registers are
described below. These registers will be in
their reset state when returning to active
mode from PM2 and PM3.
The CBC-MAC mode is a variant of the CBC
mode. When performing CBC-MAC, data is
downloaded to the coprocessor one 128 bits
SWRS033H
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