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CC1110F32RHHR 参数 Datasheet PDF下载

CC1110F32RHHR图片预览
型号: CC1110F32RHHR
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗的SoC (系统级芯片)与MCU,存储器,低于1GHz的射频收发器和USB控制器 [Low-Power SoC (System-on-Chip) with MCU, Memory, Sub-1 GHz RF Transceiver, and USB Controller]
分类和应用: 存储射频控制器
文件页数/大小: 249 页 / 3133 K
品牌: TI [ TEXAS INSTRUMENTS ]
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CC1110Fx / CC1111Fx  
12.5.2  
DMA Configuration Parameters  
Variable Length Transfer Count: When  
VLEN≠000 and VLEN≠111, the transfer count  
is given by the value of the first byte/word in  
source data, n, + a constant given by the  
VLEN setting. This allows for variable length  
transfer count.  
Setup and control of the DMA operation is  
performed by the user software. This section  
describes the parameters which must be  
configured before a DMA channel can be  
used. Section 12.5.3 on Page 105 describes  
how the parameters are set up in software and  
passed to the DMA controller.  
Note: For byte size transfers (see Section  
12.5.2.4), n is defined as the first byte in  
source data or the 7 LSB of the first byte in  
source data, depending on the M8 setting  
(see Section 12.5.2.9). For word size  
transfers, n is the 13 LSB of the first word  
in source data.  
The behavior of each of the five DMA  
channels is configured with the following  
parameters:  
12.5.2.1 Source Address (SRCADDR)  
There are four possible configurations:  
The address of the location in XDATA memory  
space where the DMA channel shall start to  
read data.  
1. VLEN=001  
Transfer  
commanded by n + 1  
number  
of  
of  
of  
of  
bytes/words  
bytes/words  
bytes/words  
bytes/words  
12.5.2.2 Destination Address (DESTADDR)  
2. VLEN=010  
The address of the location in XDATA memory  
space where the DMA channel will write the  
data read from the source address. The user  
must ensure that the destination is writable.  
Transfer  
commanded by n  
number  
3. VLEN=011  
Transfer  
commanded by n + 2  
number  
12.5.2.3 Transfer Count  
The number of bytes/words needed to be  
moved from source to destination. When the  
transfer count is reached, the DMA controller  
rearms or disarms the DMA channel  
(depending on transfer mode) and alert the  
CPU by setting the DMAIRQ.DMAIFn bit to 1.  
If IRQMASK=1, IRCON.DMAIF will also be set  
and an interrupt request is generated if  
IEN1.DMAIE=1. The transfer count can be of  
fixed or variable length depending on how the  
DMA channel is configured.  
4. VLEN=100  
Transfer  
number  
commanded by n + 3  
For all of the above configurations, the transfer  
count will be limited to LEN bytes/words when  
n ≥ LEN. In cases where n < LEN, the transfer  
count is given by the VLENsetting. This means  
that when VLEN=010, LEN should be equal to  
nmax, while in the other three cases, LEN  
should be set to nmax + 1.  
Fixed Length Transfer Count: When  
VLEN=000or VLEN=111, the transfer count is  
set by the LENsetting.  
Figure 27 shows the different VLENoptions.  
SWRS033H  
Page 103 of 246  
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