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BQ3285P 参数 Datasheet PDF下载

BQ3285P图片预览
型号: BQ3285P
PDF下载: 下载PDF文件 查看货源
内容描述: 实时时钟\n [Real-Time Clock ]
分类和应用: 时钟
文件页数/大小: 22 页 / 554 K
品牌: TI [ TEXAS INSTRUMENTS ]
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bq3285  
RS0–RS3 - Frequency Select  
Power-Down/Power-Up Cycle  
7
-
6
-
5
-
4
-
3
2
1
0
The bq3285 continuously monitors VCC for out-of-  
tolerance. During a power failure, when VCC falls below  
VPFD (4.17V typical), the bq3285 write-protects the clock  
and storage registers. When VCC is below VBC (3V typi-  
cal), the power source is switched to BC. RTC operation  
and storage data are sustained by a valid backup energy  
RS3 RS2 RS1 RS0  
These bits select one of the 13 frequencies for the SQW out-  
put and the periodic interrupt rate, as shown in Table 3.  
OS0–OS2 - Oscillator Control  
source. When VCC is above VBC, the power source is VCC  
Write-protection continues for tCSR time after VCC rises  
above VPFD  
.
7
-
6
5
4
3
-
2
-
1
-
0
-
.
OS2 OS1 OS0  
Control/Status Registers  
These three bits control the state of the oscillator and  
divider stages. A pattern of 010 enables RTC operation  
by turning on the oscillator and enabling the frequency  
divider. A pattern of 11X turns the oscillator on, but  
keeps the frequency divider disabled. When 010 is writ-  
ten, the RTC begins its first update after 500ms.  
The four control/status registers of the bq3285 are acces-  
sible regardless of the status of the update cycle (see Ta-  
ble 4).  
Register A  
UIP - Update Cycle Status  
Register A Bits  
7
6
5
4
3
2
1
0
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
UIP OS2 OS1 OS0  
RS3  
RS2 RS1 RS0  
UIP  
Register A programs:  
This read-only bit is set prior to the update cycle. When  
UIP equals 1, an RTC update cycle may be in progress.  
UIP is cleared at the end of each update cycle. This bit  
is also cleared when the update transfer inhibit (UTI)  
bit in register B is 1.  
n
n
The frequency of the square-wave and the periodic  
event rate.  
Oscillator operation.  
Register A provides:  
n
Status of the update cycle.  
Table 4. Control/Status Registers  
Bit Name and State on Reset  
Loc.  
Reg. (Hex) Read Write 7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
A
B
C
D
0A  
0B  
0C  
0D  
Yes Yes1 UIP na OS2 na OS1 na OS0 na RS3 na RS2 na RS1 na RS0 na  
Yes  
Yes  
Yes  
Yes UTI na PIE  
0
0
0
AIE  
AF  
-
0
0
0
UIE  
UF  
-
0
0
0
SQWE  
0
0
0
DF na HF na DSE na  
No INTF  
0
PF  
-
-
-
-
-
0
0
-
-
0
0
-
-
0
0
No VRT na  
Notes:  
1. Except bit 7.  
2. na = not affected  
Jan. 1999 E  
8
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