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BQ24032ARHLR 参数 Datasheet PDF下载

BQ24032ARHLR图片预览
型号: BQ24032ARHLR
PDF下载: 下载PDF文件 查看货源
内容描述: 单片充电和系统电源路径管理IC ( bqTINYTM - III ) [SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC(bqTINYTM-III)]
分类和应用: 电源电路电源管理电路PC
文件页数/大小: 32 页 / 853 K
品牌: TI [ TEXAS INSTRUMENTS ]
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bq24030, bq24031, bq24032,  
bq24032A, bq24035, bq24038, bq24039  
www.ti.com  
SLUS618CAUGUST 2004REVISED JUNE 2005  
ELECTRICAL CHARACTERISTICS (continued)  
over junction temperature range (0°C TJ 125°C) and the recommended supply voltage range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
STAT1, STAT2. ACPG AND USBPG, PG OPEN DRAIN (OD) OUTPUTS(16)  
IOL = 5 mA, An external pullup  
resistor 1 K required.  
VOL  
ILKG  
Low-level output saturation voltage  
Input leakage current  
0.25  
5
V
1
µA  
ISET2, CE, VBSEL, AND ISET3 INPUTS  
VIL  
VIH  
Low-level input voltage  
High-level input voltage  
0
0.4  
V
1.4  
Low-level input current, CE or  
ISET3  
IIL  
–1  
High-level input current, CE or  
ISET3  
IIH  
1
µA  
ms  
IIL  
Low-level input current, ISET2  
High-level input current, ISET2  
Low-level input current  
High-level input current  
Holdoff time, CE  
VISET2 = 0 V  
–20  
5
IIH  
VISET2 = VCC  
40  
1
IIL1  
VBSEL = Low  
VBSEL = High  
CE going low only  
IIH1  
15  
6
t(CE-HLDOFF)  
PSEL INPUT  
4
Falling HiLow; 280 K ± 10% applied  
when low. (bq24030/2A/5/8)  
0.975  
0
1
1.025  
0.4  
VIL  
Low-level input voltage  
High-level input voltage  
V
V
(bq24032 only)  
Input RPSEL sets external hysteresis  
(bq24030/2A/5/8)  
VIL + .01  
VIL + .024  
VIH  
(bq24032 only)  
1.4  
–1  
IIL  
Low-level input current, PSEL  
High-level input current, PSEL  
µA  
µA  
IIH  
TIMERS  
K(TMR)  
Timer set factor  
t(CHG) = K(TMR) × R(TMR)  
0.313  
30  
0.360  
0.414  
100  
s/Ω  
kΩ  
s
(17)  
R(TMR)  
External resistor limits  
Precharge timer  
t(PRECHG)  
I(FAULT)  
0.09 × t(CHG)  
0.10 × t(CHG) 0.11 × t(CHG)  
1
Timer fault recovery pullup from  
OUT to BAT  
kΩ  
CHARGER SLEEP THRESHOLDS (ACPG , PG, and USBPG THRESHOLDS, LOW POWER GOOD)  
VVCC  
VI(BAT)  
+125 mV  
V
(UVLO)VI(BAT)VO(BAT-REG)  
,
(18)  
V(SLPENT)  
Sleep-mode entry threshold  
Sleep-mode exit threshold  
No t(BOOT-UP) delay  
V
VVCC  
VI(BAT)  
+190 mV  
V(UVLO)VI(BAT)VO(BAT-REG)  
,
(18)  
V(SLPEXIT)  
No t(BOOT-UP) delay  
R(TMR) = 50 k,  
V(AC) or V(USB) or decreasing below  
threshold, 100-ns fall time, 10-mv over-  
drive  
t(DEGL)  
Deglitch time for sleep mode(19)  
22.5  
150  
ms  
ms  
START-UP CONTROL and USB BOOT-UP  
t(BOOT-UP) Boot-up time  
On the first application of USB input  
power or AC input with PSEL Low (or  
ISET3 low for bq24039)  
120  
180  
(16) See Charger Sleep mode for ACPG (VCC = VAC) and USBPS (VCC = VUSB) specifications.  
(17) To disable the safety timer and charge termination, tie TMR to the LDO pin.  
(18) The IC is considered in sleep mode when both AC and USB are absent (ACPG = USBGP = OPEN DRAIN).  
(19) Does not declare sleep mode until after the deglitch time and implement the needed power transfer immediately according to the  
switching specification.  
7
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