bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C–AUGUST 2004–REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
INPUT BIAS CURRENTS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC(SPLY)
Active supply current, VCC
VVCC > VVCC(min)
V(AC) < V(BAT), V(USB) < V(BAT)
1
2
2
5
mA
,
Sleep current (current into BAT
pin)
ICC(SLP)
2.6 V ≤ VI(BAT)≤ VO(BAT-REG)
,
Excludes load on OUT pin
VI(AC) ≤ 6V, Total current into AC pin with
ICC(AS-STDBY)
AC standby current
USB standby current
chip disabled, Excludes all loads,
CE=LOW, after t(CE-HOLDOFF) delay
200
200
Total current into USB pin with chip
disabled, Excludes all loads, CE=LOW,
after t(CE-HOLDOFF) delay
ICC(USB-STDBY)
µA
Total current into BAT pin with AC and/or
USB present and chip disabled; Ex-
cludes all loads (OUT and LDO),
CE=LOW, after t(CE-HOLDOFF) delay,
0°C ≤ TJ≤ 85°C(1)
ICC(BAT-STDBY)
BAT standby current
45
1
60
5
Charge DONE, AC or USB supplying the
load
IIB(BAT)
Charge done current, BAT
HIGH AC CUTOFF MODE
VI(AC) > 6.8 V, AC FET (Q1) turns off,
USB FET (Q3) turns on if USB power
present, otherwise BAT FET (Q2) turns
on.
Input ac cutoff voltage
(bq24039 is product preview)
VCUT-OFF
6.1
6.4
3.3
6.8
V
V
LDO OUTPUT
Active only if AC or USB is present,
VO(LDO)
Output regulation voltage
VI(OUT)≥ VO(LDO) + (IO(LDO) × RDS(on))
Regulation accuracy(2)
Output current
–5%
5%
20
50
1
IO(LDO)
RDS(on)
mA
Ω
On resistance
OUT to LDO
(3)
C(OUT)
Output capacitance
µF
OUT PIN-VOLTAGE REGULATION
bq24030/31
bq24032/2A
V
I(AC)≥ 6 V+VDO
6.0
4.4
6.3
4.5
VI(AC)≥ 4.4 V+VDO
Output
VO(OUT-REG)
regulation
voltage
V
VBSEL = HIGH or VBSEL = LOW,
VI(AC) > 4.4 V+VDO
bq24038
bq24039
4.4
6
4.5
6.3
VO(REG) + VDD-AC < VAC < VCUT-OFF
OUT PIN – DPPM REGULATION
V(DPPM-SET)
I(DPPM-SET)
SF
DPPM set point(4)
DPPM current source
DPPM scale factor
VDPPM-SET < VOUT
2.6
95
5
105
V
AC or USB present
100
µA
V(DPPM-REG)= V(DPPM-SET) × SF
1.139
1.150
1.162
(1) This includes the quiescent current for the integrated LDO.
(2) In standby mode (CE low) the accuracy is ±10%.
(3) LDO output capacitor not required but one with a value of 0.1 µF is recommended.
(4) V(DPPM-SET) is scaled up by the scale factor for controlling the output voltage V(DPPM-REG)
.
4
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