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AM6546 参数 Datasheet PDF下载

AM6546图片预览
型号: AM6546
PDF下载: 下载PDF文件 查看货源
内容描述: [具有千兆位 PRU-ICSS 的四核 Arm® Cortex®-A53 和双核 Arm Cortex-R5F Sitara™ 处理器]
分类和应用:
文件页数/大小: 286 页 / 6968 K
品牌: TI [ TEXAS INSTRUMENTS ]
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AM6548, AM6528, AM6526  
ZHCSLA7B DECEMBER 2019 REVISED JUNE 2021  
www.ti.com.cn  
6-55. PRU_ICSSG2 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
PRG2_RGMII1_TD1  
PRG2_RGMII1_TD2  
PRG2_RGMII1_TD3  
PRG2_RGMII2_RD0  
PRG2_RGMII2_RD1  
PRG2_RGMII2_RD2  
PRG2_RGMII2_RD3  
PRG2_RGMII2_TD0  
PRG2_RGMII2_TD1  
PRG2_RGMII2_TD2  
PRG2_RGMII2_TD3  
PRG2_UART0_CTSn  
PRG2_UART0_RTSn  
PRG2_UART0_RXD  
PRG2_UART0_TXD  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG UART Clear to Send (active low)  
PRU_ICSSG UART Request to Send (active low)  
PRU_ICSSG UART Receive Data  
PRU_ICSSG UART Transmit Data  
O
O
O
I
AG16  
AF16  
AE16  
AH15  
AC16  
AD17  
AH14  
AD15  
AF14  
AC15  
AD14  
AD12  
AH12  
AE12  
AF12  
I
I
I
O
O
O
O
I
O
I
O
(1) When OSC1 is being used with an external crystal, this signal is unavailable. The output functionality must be disabled.  
6.3.22 SERDES  
6.3.22.1 MAIN Domain  
6-56. SERDES0 Signal Descriptions  
see (1)  
PIN TYPE  
SIGNAL NAME [1]  
SERDES0_REFCLKN  
DESCRIPTION [2]  
SERDES Clock Input (negative)  
BALL [4]  
[3]  
I
AG5  
AG6  
AC9  
AH3  
AG2  
AH4  
AG3  
SERDES0_REFCLKP  
SERDES0_REFRES  
SERDES0_RXN  
SERDES0_RXP  
SERDES Clock Input (positive)  
SERDES Reference Resistor(2)  
I
A
I
SERDES Differential Receive Data (negative)  
SERDES Differential Receive Data (positive)  
SERDES Differential Transmit Data (negative)  
SERDES Differential Transmit Data (positive)  
I
SERDES0_TXN  
O
O
SERDES0_TXP  
(1) The functionality of these pins is controlled by CTRLMMR_SERDES0_CTRL[1:0] LANE_FUNC_SEL. 0x0 = USB3, 0x1 = PCIe0  
Lane0, 0x2 = ICSS2 SGMII Lane0.  
(2) The required resistor value is 3k±1%.  
6-57. SERDES1 Signal Descriptions  
see (1)  
PIN TYPE  
SIGNAL NAME [1]  
SERDES1_REFCLKN  
DESCRIPTION [2]  
SERDES Clock Input (negative)  
BALL [4]  
[3]  
I
AH6  
AH7  
SERDES1_REFCLKP  
SERDES1_REFRES  
SERDES1_RXN  
SERDES Clock Input (positive)  
SERDES Reference Resistor(2)  
I
A
I
AC14  
AG9  
AH10  
AH9  
SERDES Differential Receive Data (negative)  
SERDES Differential Receive Data (positive)  
SERDES Differential Transmit Data (negative)  
SERDES1_RXP  
I
SERDES1_TXN  
O
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Product Folder Links: AM6548 AM6528 AM6526  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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