AM6548, AM6528, AM6526
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021
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表6-54. PRU_ICSSG1 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
PRU_ICSSG PWM Output B
BALL [4]
[3]
PRG1_PWM3_B0
IO
IO
IO
I
AG24
AG27
AF27
AF22
AG23
AD20
AF21
AG22
AE21
AE19
AC20
AE22
AG24
AF23
AD21
AH20
AH21
AG20
AD19
AH24
AH23
AG21
AH22
AE20
AF19
AH19
AG19
AF26
AH25
AF25
AF24
PRG1_PWM3_B1
PRU_ICSSG PWM Output B
PRG1_PWM3_B2
PRU_ICSSG PWM Output B
PRG1_RGMII1_RXC
PRG1_RGMII1_RX_CTL
PRG1_RGMII1_TXC
PRG1_RGMII1_TX_CTL
PRG1_RGMII2_RXC
PRG1_RGMII2_RX_CTL
PRG1_RGMII2_TXC
PRG1_RGMII2_TX_CTL
PRG1_RGMII1_RD0
PRG1_RGMII1_RD1
PRG1_RGMII1_RD2
PRG1_RGMII1_RD3
PRG1_RGMII1_TD0
PRG1_RGMII1_TD1
PRG1_RGMII1_TD2
PRG1_RGMII1_TD3
PRG1_RGMII2_RD0
PRG1_RGMII2_RD1
PRG1_RGMII2_RD2
PRG1_RGMII2_RD3
PRG1_RGMII2_TD0
PRG1_RGMII2_TD1
PRG1_RGMII2_TD2
PRG1_RGMII2_TD3
PRG1_UART0_CTSn
PRG1_UART0_RTSn
PRG1_UART0_RXD
PRG1_UART0_TXD
PRU_ICSSG RGMII Receive Clock
PRU_ICSSG RGMII Receive Control
PRU_ICSSG RGMII Transmit Clock
PRU_ICSSG RGMII Transmit Control
PRU_ICSSG RGMII Receive Clock
PRU_ICSSG RGMII Receive Control
PRU_ICSSG RGMII Transmit Clock
PRU_ICSSG RGMII Transmit Control
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG UART Clear to Send (active low)
PRU_ICSSG UART Request to Send (active low)
PRU_ICSSG UART Receive Data
PRU_ICSSG UART Transmit Data
I
IO
O
I
I
IO
O
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
I
O
I
O
表6-55. PRU_ICSSG2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
PRU_ICSSG Enhanced Capture (ECAP) Input or
Auxiliary PWM (APWM) Ouput
PRG2_ECAP0_IN_APWM_OUT
IO
AE16
PRG2_ECAP0_SYNC_IN
PRU_ICSSG ECAP Sync Input
I
AD14
AG14
A23
PRG2_ECAP0_SYNC_OUT
PRG2_IEP0_EDIO_OUTVALID
PRU_ICSSG ECAP Sync Output
O
O(1)
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
PRG2_IEP0_EDC_LATCH_IN0
PRG2_IEP0_EDC_LATCH_IN1
PRG2_IEP0_EDC_SYNC_OUT0
I
I
AD12
AE12
AH12
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
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