AM6548, AM6528, AM6526
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021
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表6-6. VIN0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
VIN0_DATA10
VIN0_DATA11
VIN0_DATA12
VIN0_DATA13
VIN0_DATA14
VIN0_DATA15
Video Input Data 10
Video Input Data 11
Video Input Data 12
Video Input Data 13
Video Input Data 14
Video Input Data 15
I
I
I
I
I
I
R25
T27
M27
M23
M28
M24
6.3.3 CPSW2G
6.3.3.1 MCU Domain
表6-7. CPSW2G0 Signal Descriptions
PIN TYPE
SIGNAL NAME
DESCRIPTION [2]
BALL [4]
[3]
MCU_MDIO0_MDC
MCU_MDIO0_MDIO
MCU_RGMII1_RXC
MCU_RGMII1_RX_CTL
MCU_RGMII1_TXC
MCU_RGMII1_TX_CTL
MCU_RGMII1_RD0
MCU_RGMII1_RD1
MCU_RGMII1_RD2
MCU_RGMII1_RD3
MCU_RGMII1_TD0
MCU_RGMII1_TD1
MCU_RGMII1_TD2
MCU_RGMII1_TD3
MCU_RMII1_CRS_DV
MCU_RMII1_REF_CLK
MCU_RMII1_RX_ER
MCU_RMII1_TX_EN
MCU_RMII1_RXD0
MCU_RMII1_RXD1
MCU_RMII1_TXD0
MCU_RMII1_TXD1
MDIO Clock
O
IO
I
L1
L4
MDIO Data
RGMII Receive Clock
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RMII Carrier Sense / Data Valid
RMII Reference Clock
RMII Receive Data Error
RMII Transmit Enable
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
M1
N5
N1
N4
L6
I
IO
O
I
I
M6
L5
I
I
L2
O
O
O
O
I
M5
M4
M3
M2
N4
M1
N5
N1
L6
I
I
O
I
I
M6
M5
M4
O
O
6.3.4 DDRSS
6.3.4.1 MAIN Domain
表6-8. DDRSS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
DDR_AC0
DDR_AC1
DDR_AC2
DDR_AC3
DDR_AC4
DDRSS Address and Command Bus
DDRSS Address and Command Bus
DDRSS Address and Command Bus
DDRSS Address and Command Bus
DDRSS Address and Command Bus
IO
IO
IO
IO
IO
A10
D9
C9
E9
A9
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