AM6548, AM6528, AM6526
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021
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DEVICE
Selects Main PLL output divide-by-4
SYSCLK0
Optional pins to provide reference clock input to the PLLs.
Observation clock output for MCU Domain clocks
MCU_SYSCLKOUT0
MCU_OBSCLK0
WKUP_OSC0_XI
Еxternal main crystal interface pins connected to
internal oscillator whichsources reference clock.
Provides reference clock to PLLs within WKUP and MAIN domain.
WKUP_OSC0_XO
WKUP_LFOSC0_XI
Optional external low frequency crystal interface pins connected
to internal oscillator which provides a 32.768 kHz clock for
low power operation in deeper sleep modes.
WKUP_LFOSC0_XO
OSC1_XI
Optional external crystal interface pins connected to internal
oscillator which sources reference clock. Provides reference clock to
PLLs within MCU domain and MAIN domain. This high-frequency oscillator
is used to provide audio clock frequencies to MCASPs.
OSC1_XO
JTAG Clock Input
TCK
EXT_REFCLK1
Optional external System clock input (MAIN domain)
MCU Warm Reset Input / Device Warm Reset Input
MCU_RESETz/ RESETz
MCU_PORz / PORz
MCU Power ON Reset / Device Power ON Reset
Boot Mode Configuration / devices select
BOOTMODE[18:00]
MCU_BOOTMODE[09:00]
DDR_CK0P/DDR_CK0N
DDR_CK1P/DDR_CK1N
MCU Boot Mode system clock speed and fail-safe boot device
DDR Differential Clock outputs
REFCLK0 P/N
REFCLK1 P/N
There are 2 differential clock output pins to support 2 PCIe
devices
Observation clock output for MAIN and MCU Domain clocks
SerDes reference clock input for PCIe or Optional USB3SS0 PHY
OBSCLK0
SERDES0_REFCLK P/N
SERDES1_REFCLK P/N
MCU_CPTS0_RFT_CLK
CPTS reference clock input for MCU_CPTS_RFT_CLK
MCU_EXT_REFCLK0
VOUT1_EXTPCLKIN
CPTS0_RFT_CLK
Optional external system clock input (MCU domain)
Optional for the DPI1 Port of DSS
CPTS reference clock input for CPTS_RFT_CLK
SPRSP08_CLOCK_01
图7-14. Input Clocks Interface
For more information about Input clock interfaces, see the Clocking section in the device TRM.
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