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AM6546 参数 Datasheet PDF下载

AM6546图片预览
型号: AM6546
PDF下载: 下载PDF文件 查看货源
内容描述: [具有千兆位 PRU-ICSS 的四核 Arm® Cortex®-A53 和双核 Arm Cortex-R5F Sitara™ 处理器]
分类和应用:
文件页数/大小: 286 页 / 6968 K
品牌: TI [ TEXAS INSTRUMENTS ]
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AM6548, AM6528, AM6526  
ZHCSLA7B DECEMBER 2019 REVISED JUNE 2021  
www.ti.com.cn  
7.9.3.3 Clock Timing  
Tables and figures provided in this section define timing requirements and switching characteristics for clock  
signals.  
7-12. Clock Timing Requirements  
see 7-12  
NO.  
MIN  
18.52  
MAX UNIT  
CLK1 tc(EXT_REFCLK1)  
CLK2 tw(EXT_REFCLK1H)  
CLK3 tw(EXT_REFCLK1L)  
CLK13 tc(MCU_EXT_REFCLK0)  
CLK14 tw(MCU_EXT_REFCLK0H)  
CLK15 tw(MCU_EXT_REFCLK0L)  
Cycle time, EXT_REFCLK1  
ns  
Pulse Duration, EXT_REFCLK1 high  
Pulse Duration, EXT_REFCLK1 low  
Cycle time, MCU_EXT_REFCLK0  
Pulse Duration, MCU_EXT_REFCLK0 high  
Pulse Duration, MCU_EXT_REFCLK0 low  
E*0.45(1)  
E*0.45(1)  
18.52  
E*0.55(1)  
ns  
ns  
ns  
ns  
ns  
E*0.55(1)  
F*0.45(2)  
F*0.45(2)  
F*0.55(2)  
F*0.55(2)  
(1) E = EXT_REFCLK1 cycle time.  
(2) F = MCU_EXT_REFCLK0 cycle time.  
7-12. Clock Timing Requirements  
7-13. Clock Switching Characteristics  
see 7-13  
NO.  
PARAMETER  
MIN  
6
MAX UNIT  
CLK4 tc(SYSCLKOUT0)  
CLK5 tw(SYSCLKOUT0H)  
CLK6 tw(SYSCLKOUT0L)  
CLK7 tc(OBSCLK0)  
Cycle time minimum,SYSCLKOUT0  
Pulse Duration minimum, SYSCLKOUT0 high  
Pulse Duration minimum, SYSCLKOUT0 low  
Cycle time minimum, OBSCLK0  
ns  
A*0.4(1)  
A*0.4(1)  
5
A*0.6(1)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
A*0.6(1)  
CLK8 tw(OBSCLK0H)  
CLK9 tw(OBSCLK0L)  
CLK10 tc(CLKOUT0)  
Pulse Duration minimum, OBSCLK0 high  
Pulse Duration minimum,OBSCLK0 low  
Cycle time minimum, MCU_CLKOUT0  
Pulse Duration minimum, MCU_CLKOUT0 high  
Pulse Duration minimum,MCU_CLKOUT0 low  
Cycle time minimum,MCU_SYSCLKOUT0  
B*0.45(2)  
B*0.45(2)  
20  
B*0.55(2)  
B*0.55(2)  
40  
CLK11 tw(CLKOUT0H)  
CLK12 tw(CLKOUT0L)  
CLK16 tc(MCU_SYSCLKOUT0)  
C*0.4(3)  
C*0.4(3)  
6
C*0.6(3)  
C*0.6(3)  
Pulse Duration minimum, MCU_SYSCLKOUT0  
high  
CLK17 tw(MCU_SYSCLKOUT0H)  
A*0.4(1)  
A*0.6(1)  
A*0.6(1)  
ns  
CLK18 tw(MCU_SYSCLKOUT0L)  
CLK19 tc(MCU_OBSCLK0)  
CLK20 tw(MCU_OBSCLK0H)  
CLK21 tw(MCU_OBSCLK0L)  
Pulse Duration minimum, MCU_SYSCLKOUT0 low  
Cycle time minimum, MCU_OBSCLK0  
A*0.4(1)  
5
ns  
ns  
ns  
ns  
Pulse Duration minimum, MCU_OBSCLK0 high  
Pulse Duration minimum,MCU_OBSCLK0 low  
B*0.45(2)  
B*0.45(2)  
B*0.55(2)  
B*0.55(2)  
(1) A = SYSCLKOUT0 cycle time in MAIN domain; A = MCU_SYSCLKOUT0 in MCU domain.  
(2) B = OBSCLK0 cycle time in MAIN domain; B = MCU_OBSCLK0 in MCU domain.  
(3) C = MCU_CLKOUT0 cycle time.  
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Product Folder Links: AM6548 AM6528 AM6526  
 
 
 
 
 
 
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