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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
Table 3-5. VDD_CORE Operating Performance Points for ZCE Package
with Device Revision Code "Blank"(1)
VDD_CORE
OPP
Device Rev.
"Blank"
VDD_MPU(2)
NOM
DDR3,
ARM (A8)
DDR2(3)
mDDR(3)
L3 and L4
DDR3L(3)
MIN
MAX
OPP100
1.056 V
1.100 V
1.144 V
1.144 V
500 MHz
275 MHz
400 MHz
400 MHz
266 MHz
266 MHz
200 MHz
200 MHz
200 MHz and
100 MHz
OPP100
1.056 V
1.100 V
200 MHz and
100 MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) VDD_MPU is merged with VDD_CORE on the ZCE package.
(3) This parameter represents the maximum memory clock frequency. Since data is transferred on both edges of the clock, double-data rate
(DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
Copyright © 2011–2013, Texas Instruments Incorporated
Device Operating Conditions
83
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