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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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Table 2-49. GEMAC_CPSW/RGMII1 Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
rgmii1_rctl
rgmii1_rd0
rgmii1_rd1
rgmii1_rd2
rgmii1_rd3
RGMII Receive Control
I
I
I
I
I
L19
J17
RGMII Receive Data bit 0
RGMII Receive Data bit 1
RGMII Receive Data bit 2
RGMII Receive Data bit 3
RGMII Transmit Clock
P18
P19
N16
N17
N19
K17
L18
M18
N18
M17
M16
L15
L16
L17
K18
J16
K17
K16
K15
J18
rgmii1_tclk
rgmii1_tctl
rgmii1_td0
rgmii1_td1
rgmii1_td2
rgmii1_td3
O
O
O
O
O
O
RGMII Transmit Control
RGMII Transmit Data bit 0
RGMII Transmit Data bit 1
RGMII Transmit Data bit 2
RGMII Transmit Data bit 3
Table 2-50. GEMAC_CPSW/RGMII2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
RGMII Receive Clock
ZCE BALL [4]
ZCZ BALL [4]
rgmii2_rclk
rgmii2_rctl
rgmii2_rd0
rgmii2_rd1
rgmii2_rd2
rgmii2_rd3
rgmii2_tclk
rgmii2_tctl
rgmii2_td0
rgmii2_td1
rgmii2_td2
rgmii2_td3
I
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
T15
V14
V17
T16
U16
V16
U15
R13
V15
R14
T14
U14
RGMII Receive Control
RGMII Receive Data bit 0
RGMII Receive Data bit 1
RGMII Receive Data bit 2
RGMII Receive Data bit 3
RGMII Transmit Clock
I
I
I
I
I
O
O
O
O
O
O
RGMII Transmit Control
RGMII Transmit Data bit 0
RGMII Transmit Data bit 1
RGMII Transmit Data bit 2
RGMII Transmit Data bit 3
Table 2-51. GEMAC_CPSW/RMII1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
rmii1_crs_dv
rmii1_refclk
rmii1_rxd0
rmii1_rxd1
rmii1_rxer
rmii1_txd0
rmii1_txd1
rmii1_txen
RMII Carrier Sense / Data Valid
RMII Reference Clock
I
J18
K18
P18
P19
K19
L18
M18
K17
H17
H18
M16
L15
J15
K17
K16
J16
I/O
I
RMII Receive Data bit 0
RMII Receive Data bit 1
RMII Receive Data Error
RMII Transmit Data bit 0
RMII Transmit Data bit 1
RMII Transmit Enable
I
I
O
O
O
Table 2-52. GEMAC_CPSW/RMII2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
rmii2_crs_dv
rmii2_refclk
rmii2_rxd0
rmii2_rxd1
RMII Carrier Sense / Data Valid
RMII Reference Clock
I
R15, U17
J19
T13, T17
H16
I/O
RMII Receive Data bit 0
RMII Receive Data bit 1
I
I
NA
V17
NA
T16
72
Terminal Description
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