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AM3356, AM3354, AM3352
SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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Table 2-34. PRU-ICSS/MII0 Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
pr1_mii0_rxlink
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
MII Receive Link
I
V6
V2
pr1_mii0_txd0
pr1_mii0_txd1
pr1_mii0_txd2
pr1_mii0_txd3
pr1_mii0_txen
pr1_mii_mr0_clk
pr1_mii_mt0_clk
MII Transmit Data bit 0
MII Transmit Data bit 1
MII Transmit Data bit 2
MII Transmit Data bit 3
MII Transmit Enable
MII Receive Clock
O
O
O
O
O
I
W17, W3
T13, W2
U13, V2
U12, V1
T12, U2
W6
T2, V13
R12, T1
R4, T12
R3, U12
R2, T11
V4
MII Transmit Clock
I
U1, V15
R1, U10
Table 2-35. PRU-ICSS/MII1 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
pr1_mii1_col
MII Collision Detect
MII Carrier Sense
I
R15
V16, W7
NA
T17
pr1_mii1_crs
I
R6, V12
V16
T15
pr1_mii1_rxd0
pr1_mii1_rxd1
pr1_mii1_rxd2
pr1_mii1_rxd3
pr1_mii1_rxdv
pr1_mii1_rxer
pr1_mii1_rxlink
pr1_mii1_txd0
pr1_mii1_txd1
pr1_mii1_txd2
pr1_mii1_txd3
pr1_mii1_txen
pr1_mii_mr1_clk
pr1_mii_mt1_clk
MII Receive Data bit 0
MII Receive Data bit 1
MII Receive Data bit 2
MII Receive Data bit 3
MII Receive Data Valid
MII Receive Data Error
MII Receive Link
I
I
NA
I
NA
U15
V15
T16
I
NA
I
NA
I
NA
V17
U18
R14
T14
I
V18
NA
MII Transmit Data bit 0
MII Transmit Data bit 1
MII Transmit Data bit 2
MII Transmit Data bit 3
MII Transmit Enable
MII Receive Clock
O
O
O
O
O
I
NA
NA
U14
V14
U17
U16
R13
NA
W18
NA
MII Transmit Clock
I
NA
Table 2-36. PRU-ICSS/UART0 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
pr1_uart0_cts_n
pr1_uart0_rts_n
pr1_uart0_rxd
pr1_uart0_txd
UART Clear to Send
UART Request to Send
UART Receive Data
UART Transmit Data
I
A18, E17
B18, D19
B17, D18
A17, C19
A17, D18
B17, D17
B16, D16
A16, D15
O
I
O
66
Terminal Description
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